Optimized High Speed NRF24L01+ Driver Class Documenation  V1.0
TMRh20 2014 - Optimized Fork of NRF24L01+ Driver
RF24.cpp
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1 /*
2  Copyright (C) 2011 J. Coliz <maniacbug@ymail.com>
3 
4  This program is free software; you can redistribute it and/or
5  modify it under the terms of the GNU General Public License
6  version 2 as published by the Free Software Foundation.
7  */
8 
9 #include "nRF24L01.h"
10 #include "RF24_config.h"
11 #include "RF24.h"
12 
13 /****************************************************************************/
14 
15 void RF24::csn(bool mode)
16 {
17 
18 #if defined (RF24_TINY)
19  if (ce_pin != csn_pin) {
20  digitalWrite(csn_pin,mode);
21  }
22  else {
23  if (mode == HIGH) {
24  PORTB |= (1<<PINB2); // SCK->CSN HIGH
25  delayMicroseconds(100); // allow csn to settle.
26  }
27  else {
28  PORTB &= ~(1<<PINB2); // SCK->CSN LOW
29  delayMicroseconds(11); // allow csn to settle
30  }
31  }
32  // Return, CSN toggle complete
33  return;
34 
35 #elif defined(ARDUINO) && !defined (RF24_SPI_TRANSACTIONS)
36  // Minimum ideal SPI bus speed is 2x data rate
37  // If we assume 2Mbs data rate and 16Mhz clock, a
38  // divider of 4 is the minimum we want.
39  // CLK:BUS 8Mhz:2Mhz, 16Mhz:4Mhz, or 20Mhz:5Mhz
40 
41  #if !defined (SOFTSPI)
42  _SPI.setBitOrder(MSBFIRST);
43  _SPI.setDataMode(SPI_MODE0);
44  _SPI.setClockDivider(SPI_CLOCK_DIV2);
45  #endif
46 #elif defined (RF24_RPi)
47  if(!mode)
48  _SPI.chipSelect(csn_pin);
49 #endif
50 
51 #if !defined (RF24_LINUX)
52  digitalWrite(csn_pin,mode);
54 #endif
55 
56 }
57 
58 /****************************************************************************/
59 
60 void RF24::ce(bool level)
61 {
62  //Allow for 3-pin use on ATTiny
63  if (ce_pin != csn_pin) digitalWrite(ce_pin,level);
64 }
65 
66 /****************************************************************************/
67 
68  inline void RF24::beginTransaction() {
69  #if defined (RF24_SPI_TRANSACTIONS)
70  _SPI.beginTransaction(SPISettings(RF24_SPI_SPEED, MSBFIRST, SPI_MODE0));
71  #endif
72  csn(LOW);
73  }
74 
75 /****************************************************************************/
76 
77  inline void RF24::endTransaction() {
78  csn(HIGH);
79  #if defined (RF24_SPI_TRANSACTIONS)
80  _SPI.endTransaction();
81  #endif
82  }
83 
84 /****************************************************************************/
85 
86 uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
87 {
88  uint8_t status;
89 
90  #if defined (RF24_LINUX)
91  beginTransaction(); //configures the spi settings for RPi, locks mutex and setting csn low
92  uint8_t * prx = spi_rxbuff;
93  uint8_t * ptx = spi_txbuff;
94  uint8_t size = len + 1; // Add register value to transmit buffer
95 
96  *ptx++ = ( R_REGISTER | ( REGISTER_MASK & reg ) );
97 
98  while (len--){ *ptx++ = NOP; } // Dummy operation, just for reading
99 
100  _SPI.transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, size);
101 
102  status = *prx++; // status is 1st byte of receive buffer
103 
104  // decrement before to skip status byte
105  while ( --size ){ *buf++ = *prx++; }
106  endTransaction(); //unlocks mutex and setting csn high
107 
108 #else
109 
111  status = _SPI.transfer( R_REGISTER | ( REGISTER_MASK & reg ) );
112  while ( len-- ){
113  *buf++ = _SPI.transfer(0xff);
114  }
115  endTransaction();
116 
117 #endif
118 
119  return status;
120 }
121 
122 /****************************************************************************/
123 
124 uint8_t RF24::read_register(uint8_t reg)
125 {
126  uint8_t result;
127 
128  #if defined (RF24_LINUX)
129 
131 
132  uint8_t * prx = spi_rxbuff;
133  uint8_t * ptx = spi_txbuff;
134  *ptx++ = ( R_REGISTER | ( REGISTER_MASK & reg ) );
135  *ptx++ = NOP ; // Dummy operation, just for reading
136 
137  _SPI.transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, 2);
138  result = *++prx; // result is 2nd byte of receive buffer
139 
140  endTransaction();
141  #else
142 
144  _SPI.transfer( R_REGISTER | ( REGISTER_MASK & reg ) );
145  result = _SPI.transfer(0xff);
146  endTransaction();
147 
148  #endif
149 
150  return result;
151 }
152 
153 /****************************************************************************/
154 
155 uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
156 {
157  uint8_t status;
158 
159  #if defined (RF24_LINUX)
161  uint8_t * prx = spi_rxbuff;
162  uint8_t * ptx = spi_txbuff;
163  uint8_t size = len + 1; // Add register value to transmit buffer
164 
165  *ptx++ = ( W_REGISTER | ( REGISTER_MASK & reg ) );
166  while ( len-- )
167  *ptx++ = *buf++;
168 
169  _SPI.transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, size);
170  status = *prx; // status is 1st byte of receive buffer
171  endTransaction();
172  #else
173 
175  status = _SPI.transfer( W_REGISTER | ( REGISTER_MASK & reg ) );
176  while ( len-- )
177  _SPI.transfer(*buf++);
178  endTransaction();
179 
180  #endif
181 
182  return status;
183 }
184 
185 /****************************************************************************/
186 
187 uint8_t RF24::write_register(uint8_t reg, uint8_t value)
188 {
189  uint8_t status;
190 
191  IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\r\n"),reg,value));
192 
193  #if defined (RF24_LINUX)
195  uint8_t * prx = spi_rxbuff;
196  uint8_t * ptx = spi_txbuff;
197  *ptx++ = ( W_REGISTER | ( REGISTER_MASK & reg ) );
198  *ptx = value ;
199 
200  _SPI.transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, 2);
201  status = *prx++; // status is 1st byte of receive buffer
202  endTransaction();
203  #else
204 
206  status = _SPI.transfer( W_REGISTER | ( REGISTER_MASK & reg ) );
207  _SPI.transfer(value);
208  endTransaction();
209 
210  #endif
211 
212  return status;
213 }
214 
215 /****************************************************************************/
216 
217 uint8_t RF24::write_payload(const void* buf, uint8_t data_len, const uint8_t writeType)
218 {
219  uint8_t status;
220  const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
221 
222  data_len = rf24_min(data_len, payload_size);
223  uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
224 
225  //printf("[Writing %u bytes %u blanks]",data_len,blank_len);
226  IF_SERIAL_DEBUG( printf("[Writing %u bytes %u blanks]\n",data_len,blank_len); );
227 
228  #if defined (RF24_LINUX)
230  uint8_t * prx = spi_rxbuff;
231  uint8_t * ptx = spi_txbuff;
232  uint8_t size;
233  size = data_len + blank_len + 1 ; // Add register value to transmit buffer
234 
235  *ptx++ = writeType;
236  while ( data_len-- )
237  *ptx++ = *current++;
238  while ( blank_len-- )
239  *ptx++ = 0;
240 
241  _SPI.transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, size);
242  status = *prx; // status is 1st byte of receive buffer
243  endTransaction();
244 
245  #else
246 
248  status = _SPI.transfer( writeType );
249  while ( data_len-- ) {
250  _SPI.transfer(*current++);
251  }
252  while ( blank_len-- ) {
253  _SPI.transfer(0);
254  }
255  endTransaction();
256 
257  #endif
258 
259  return status;
260 }
261 
262 /****************************************************************************/
263 
264 uint8_t RF24::read_payload(void* buf, uint8_t data_len)
265 {
266  uint8_t status;
267  uint8_t* current = reinterpret_cast<uint8_t*>(buf);
268 
269  if(data_len > payload_size) data_len = payload_size;
270  uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
271 
272  //printf("[Reading %u bytes %u blanks]",data_len,blank_len);
273 
274  IF_SERIAL_DEBUG( printf("[Reading %u bytes %u blanks]\n",data_len,blank_len); );
275 
276  #if defined (RF24_LINUX)
278  uint8_t * prx = spi_rxbuff;
279  uint8_t * ptx = spi_txbuff;
280  uint8_t size;
281  size = data_len + blank_len + 1; // Add register value to transmit buffer
282 
283  *ptx++ = R_RX_PAYLOAD;
284  while(--size)
285  *ptx++ = NOP;
286 
287  size = data_len + blank_len + 1; // Size has been lost during while, re affect
288 
289  _SPI.transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, size);
290 
291  status = *prx++; // 1st byte is status
292 
293  if (data_len > 0) {
294  while ( --data_len ) // Decrement before to skip 1st status byte
295  *current++ = *prx++;
296 
297  *current = *prx;
298  }
299  endTransaction();
300  #else
301 
303  status = _SPI.transfer( R_RX_PAYLOAD );
304  while ( data_len-- ) {
305  *current++ = _SPI.transfer(0xFF);
306  }
307  while ( blank_len-- ) {
308  _SPI.transfer(0xff);
309  }
310  endTransaction();
311 
312  #endif
313 
314  return status;
315 }
316 
317 /****************************************************************************/
318 
319 uint8_t RF24::flush_rx(void)
320 {
321  return spiTrans( FLUSH_RX );
322 }
323 
324 /****************************************************************************/
325 
326 uint8_t RF24::flush_tx(void)
327 {
328  return spiTrans( FLUSH_TX );
329 }
330 
331 /****************************************************************************/
332 
333 uint8_t RF24::spiTrans(uint8_t cmd){
334 
335  uint8_t status;
336 
338  status = _SPI.transfer( cmd );
339  endTransaction();
340 
341  return status;
342 }
343 
344 /****************************************************************************/
345 
346 uint8_t RF24::get_status(void)
347 {
348  return spiTrans(NOP);
349 }
350 
351 /****************************************************************************/
352 #if !defined (MINIMAL)
353 void RF24::print_status(uint8_t status)
354 {
355  printf_P(PSTR("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n"),
356  status,
357  (status & _BV(RX_DR))?1:0,
358  (status & _BV(TX_DS))?1:0,
359  (status & _BV(MAX_RT))?1:0,
360  ((status >> RX_P_NO) & 0b111),
361  (status & _BV(TX_FULL))?1:0
362  );
363 }
364 
365 /****************************************************************************/
366 
367 void RF24::print_observe_tx(uint8_t value)
368 {
369  printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"),
370  value,
371  (value >> PLOS_CNT) & 0b1111,
372  (value >> ARC_CNT) & 0b1111
373  );
374 }
375 
376 /****************************************************************************/
377 
378 void RF24::print_byte_register(const char* name, uint8_t reg, uint8_t qty)
379 {
380  //char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
381  //printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab);
382  #if defined (RF24_LINUX)
383  printf("%s\t =", name);
384  #else
385  printf_P(PSTR(PRIPSTR"\t ="),name);
386  #endif
387  while (qty--)
388  printf_P(PSTR(" 0x%02x"),read_register(reg++));
389  printf_P(PSTR("\r\n"));
390 }
391 
392 /****************************************************************************/
393 
394 void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty)
395 {
396 
397  #if defined (RF24_LINUX)
398  printf("%s\t =",name);
399  #else
400  printf_P(PSTR(PRIPSTR"\t ="),name);
401  #endif
402  while (qty--)
403  {
404  uint8_t buffer[addr_width];
405  read_register(reg++,buffer,sizeof buffer);
406 
407  printf_P(PSTR(" 0x"));
408  uint8_t* bufptr = buffer + sizeof buffer;
409  while( --bufptr >= buffer )
410  printf_P(PSTR("%02x"),*bufptr);
411  }
412 
413  printf_P(PSTR("\r\n"));
414 }
415 #endif
416 /****************************************************************************/
417 
418 RF24::RF24(uint8_t _cepin, uint8_t _cspin):
419  ce_pin(_cepin), csn_pin(_cspin), p_variant(false),
420  payload_size(32), dynamic_payloads_enabled(false), addr_width(5)//,pipe0_reading_address(0)
421 {
422  pipe0_reading_address[0]=0;
423 }
424 
425 /****************************************************************************/
426 
427 #if defined (RF24_LINUX) && !defined (MRAA)//RPi constructor
428 RF24::RF24(uint8_t _cepin, uint8_t _cspin, uint32_t _spi_speed):
429  ce_pin(_cepin),csn_pin(_cspin),spi_speed(_spi_speed),p_variant(false), payload_size(32), dynamic_payloads_enabled(false),addr_width(5)//,pipe0_reading_address(0)
430 {
431  pipe0_reading_address[0]=0;
432 }
433 #endif
434 
435 /****************************************************************************/
436 
437 void RF24::setChannel(uint8_t channel)
438 {
439  const uint8_t max_channel = 125;
440  write_register(RF_CH,rf24_min(channel,max_channel));
441 }
442 
444 {
445 
446  return read_register(RF_CH);
447 }
448 /****************************************************************************/
449 
450 void RF24::setPayloadSize(uint8_t size)
451 {
452  payload_size = rf24_min(size,32);
453 }
454 
455 /****************************************************************************/
456 
457 uint8_t RF24::getPayloadSize(void)
458 {
459  return payload_size;
460 }
461 
462 /****************************************************************************/
463 
464 #if !defined (MINIMAL)
465 
466 static const char rf24_datarate_e_str_0[] PROGMEM = "1MBPS";
467 static const char rf24_datarate_e_str_1[] PROGMEM = "2MBPS";
468 static const char rf24_datarate_e_str_2[] PROGMEM = "250KBPS";
469 static const char * const rf24_datarate_e_str_P[] PROGMEM = {
470  rf24_datarate_e_str_0,
471  rf24_datarate_e_str_1,
472  rf24_datarate_e_str_2,
473 };
474 static const char rf24_model_e_str_0[] PROGMEM = "nRF24L01";
475 static const char rf24_model_e_str_1[] PROGMEM = "nRF24L01+";
476 static const char * const rf24_model_e_str_P[] PROGMEM = {
477  rf24_model_e_str_0,
478  rf24_model_e_str_1,
479 };
480 static const char rf24_crclength_e_str_0[] PROGMEM = "Disabled";
481 static const char rf24_crclength_e_str_1[] PROGMEM = "8 bits";
482 static const char rf24_crclength_e_str_2[] PROGMEM = "16 bits" ;
483 static const char * const rf24_crclength_e_str_P[] PROGMEM = {
484  rf24_crclength_e_str_0,
485  rf24_crclength_e_str_1,
486  rf24_crclength_e_str_2,
487 };
488 static const char rf24_pa_dbm_e_str_0[] PROGMEM = "PA_MIN";
489 static const char rf24_pa_dbm_e_str_1[] PROGMEM = "PA_LOW";
490 static const char rf24_pa_dbm_e_str_2[] PROGMEM = "PA_HIGH";
491 static const char rf24_pa_dbm_e_str_3[] PROGMEM = "PA_MAX";
492 static const char * const rf24_pa_dbm_e_str_P[] PROGMEM = {
493  rf24_pa_dbm_e_str_0,
494  rf24_pa_dbm_e_str_1,
495  rf24_pa_dbm_e_str_2,
496  rf24_pa_dbm_e_str_3,
497 };
498 
499 #if defined (RF24_LINUX)
500 static const char rf24_csn_e_str_0[] = "CE0 (PI Hardware Driven)";
501 static const char rf24_csn_e_str_1[] = "CE1 (PI Hardware Driven)";
502 static const char rf24_csn_e_str_2[] = "CE2 (PI Hardware Driven)";
503 static const char rf24_csn_e_str_3[] = "Custom GPIO Software Driven";
504 static const char * const rf24_csn_e_str_P[] = {
505  rf24_csn_e_str_0,
506  rf24_csn_e_str_1,
507  rf24_csn_e_str_2,
508  rf24_csn_e_str_3,
509 };
510 #endif
511 
513 {
514 
515 #if defined (RF24_RPi)
516  printf("================ SPI Configuration ================\n" );
517  if (csn_pin < BCM2835_SPI_CS_NONE ){
518  printf("CSN Pin \t = %s\n",rf24_csn_e_str_P[csn_pin]);
519  }else{
520  printf("CSN Pin \t = Custom GPIO%d%s\n", csn_pin,
521  csn_pin==RPI_V2_GPIO_P1_26 ? " (CE1) Software Driven" : "" );
522  }
523  printf("CE Pin \t = Custom GPIO%d\n", ce_pin );
524  printf("Clock Speed\t = " );
525  switch (spi_speed)
526  {
527  case BCM2835_SPI_SPEED_64MHZ : printf("64 Mhz"); break ;
528  case BCM2835_SPI_SPEED_32MHZ : printf("32 Mhz"); break ;
529  case BCM2835_SPI_SPEED_16MHZ : printf("16 Mhz"); break ;
530  case BCM2835_SPI_SPEED_8MHZ : printf("8 Mhz"); break ;
531  case BCM2835_SPI_SPEED_4MHZ : printf("4 Mhz"); break ;
532  case BCM2835_SPI_SPEED_2MHZ : printf("2 Mhz"); break ;
533  case BCM2835_SPI_SPEED_1MHZ : printf("1 Mhz"); break ;
534  case BCM2835_SPI_SPEED_512KHZ: printf("512 KHz"); break ;
535  case BCM2835_SPI_SPEED_256KHZ: printf("256 KHz"); break ;
536  case BCM2835_SPI_SPEED_128KHZ: printf("128 KHz"); break ;
537  case BCM2835_SPI_SPEED_64KHZ : printf("64 KHz"); break ;
538  case BCM2835_SPI_SPEED_32KHZ : printf("32 KHz"); break ;
539  case BCM2835_SPI_SPEED_16KHZ : printf("16 KHz"); break ;
540  case BCM2835_SPI_SPEED_8KHZ : printf("8 KHz"); break ;
541  default : printf("8 Mhz"); break ;
542  }
543  printf("\n================ NRF Configuration ================\n");
544 
545 #endif //Linux
546 
547  print_status(get_status());
548 
549  print_address_register(PSTR("RX_ADDR_P0-1"),RX_ADDR_P0,2);
550  print_byte_register(PSTR("RX_ADDR_P2-5"),RX_ADDR_P2,4);
551  print_address_register(PSTR("TX_ADDR\t"),TX_ADDR);
552 
553  print_byte_register(PSTR("RX_PW_P0-6"),RX_PW_P0,6);
554  print_byte_register(PSTR("EN_AA\t"),EN_AA);
555  print_byte_register(PSTR("EN_RXADDR"),EN_RXADDR);
556  print_byte_register(PSTR("RF_CH\t"),RF_CH);
557  print_byte_register(PSTR("RF_SETUP"),RF_SETUP);
558  print_byte_register(PSTR("CONFIG\t"),NRF_CONFIG);
559  print_byte_register(PSTR("DYNPD/FEATURE"),DYNPD,2);
560 
561  printf_P(PSTR("Data Rate\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_datarate_e_str_P[getDataRate()]));
562  printf_P(PSTR("Model\t\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_model_e_str_P[isPVariant()]));
563  printf_P(PSTR("CRC Length\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_crclength_e_str_P[getCRCLength()]));
564  printf_P(PSTR("PA Power\t = " PRIPSTR "\r\n"), pgm_read_word(&rf24_pa_dbm_e_str_P[getPALevel()]));
565 
566 }
567 
568 #endif
569 /****************************************************************************/
570 
571 bool RF24::begin(void)
572 {
573 
574  uint8_t setup=0;
575 
576  #if defined (RF24_LINUX)
577 
578  #if defined (MRAA)
579  GPIO();
580  gpio.begin(ce_pin,csn_pin);
581  #endif
582 
583  #ifdef RF24_RPi
584  switch(csn_pin){ //Ensure valid hardware CS pin
585  case 0: break;
586  case 1: break;
587  // Allow BCM2835 enums for RPi
588  case 8: csn_pin = 0; break;
589  case 7: csn_pin = 1; break;
590  default: csn_pin = 0; break;
591  }
592  #endif
593 
594  _SPI.begin(csn_pin);
595 
596  pinMode(ce_pin,OUTPUT);
597  ce(LOW);
598 
599  delay(100);
600 
601  #elif defined(LITTLEWIRE)
602  pinMode(csn_pin,OUTPUT);
603  _SPI.begin();
604  csn(HIGH);
605  #elif defined(XMEGA_D3)
606  if (ce_pin != csn_pin) pinMode(ce_pin,OUTPUT);
607  _SPI.begin(csn_pin);
608  ce(LOW);
609  csn(HIGH);
610  delay(200);
611  #else
612  // Initialize pins
613  if (ce_pin != csn_pin) pinMode(ce_pin,OUTPUT);
614 
615  #if ! defined(LITTLEWIRE)
616  if (ce_pin != csn_pin)
617  #endif
618  pinMode(csn_pin,OUTPUT);
619 
620  _SPI.begin();
621  ce(LOW);
622  csn(HIGH);
623  #if defined (__ARDUINO_X86__)
624  delay(100);
625  #endif
626  #endif //Linux
627 
628  // Must allow the radio time to settle else configuration bits will not necessarily stick.
629  // This is actually only required following power up but some settling time also appears to
630  // be required after resets too. For full coverage, we'll always assume the worst.
631  // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped.
632  // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure.
633  // WARNING: Delay is based on P-variant whereby non-P *may* require different timing.
634  delay( 5 ) ;
635 
636  // Reset NRF_CONFIG and enable 16-bit CRC.
637  write_register( NRF_CONFIG, 0b00001100 ) ;
638 
639  // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
640  // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
641  // sizes must never be used. See documentation for a more complete explanation.
642  setRetries(5,15);
643 
644  // Reset value is MAX
645  //setPALevel( RF24_PA_MAX ) ;
646 
647  // check for connected module and if this is a p nRF24l01 variant
648  //
649  if( setDataRate( RF24_250KBPS ) )
650  {
651  p_variant = true ;
652  }
653  setup = read_register(RF_SETUP);
654  /*if( setup == 0b00001110 ) // register default for nRF24L01P
655  {
656  p_variant = true ;
657  }*/
658 
659  // Then set the data rate to the slowest (and most reliable) speed supported by all
660  // hardware.
662 
663  // Initialize CRC and request 2-byte (16bit) CRC
664  //setCRCLength( RF24_CRC_16 ) ;
665 
666  // Disable dynamic payloads, to match dynamic_payloads_enabled setting - Reset value is 0
667  toggle_features();
668  write_register(FEATURE,0 );
669  write_register(DYNPD,0);
670 
671  // Reset current status
672  // Notice reset and flush is the last thing we do
673  write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
674 
675  // Set up default configuration. Callers can always change it later.
676  // This channel should be universally safe and not bleed over into adjacent
677  // spectrum.
678  setChannel(76);
679 
680  // Flush buffers
681  flush_rx();
682  flush_tx();
683 
684  powerUp(); //Power up by default when begin() is called
685 
686  // Enable PTX, do not write CE high so radio will remain in standby I mode ( 130us max to transition to RX or TX instead of 1500us from powerUp )
687  // PTX should use only 22uA of power
688  write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) );
689 
690  // if setup is 0 or ff then there was no response from module
691  return ( setup != 0 && setup != 0xff );
692 }
693 
694 /****************************************************************************/
695 
697 {
698  #if !defined (RF24_TINY) && ! defined(LITTLEWIRE)
699  powerUp();
700  #endif
701  write_register(NRF_CONFIG, read_register(NRF_CONFIG) | _BV(PRIM_RX));
702  write_register(NRF_STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
703  ce(HIGH);
704  // Restore the pipe0 adddress, if exists
705  if (pipe0_reading_address[0] > 0){
706  write_register(RX_ADDR_P0, pipe0_reading_address, addr_width);
707  }else{
708  closeReadingPipe(0);
709  }
710 
711  // Flush buffers
712  //flush_rx();
713  if(read_register(FEATURE) & _BV(EN_ACK_PAY)){
714  flush_tx();
715  }
716 
717  // Go!
718  //delayMicroseconds(100);
719 }
720 
721 /****************************************************************************/
722 static const uint8_t child_pipe_enable[] PROGMEM =
723 {
725 };
726 
728 {
729  ce(LOW);
730 
732 
733  if(read_register(FEATURE) & _BV(EN_ACK_PAY)){
734  delayMicroseconds(txDelay); //200
735  flush_tx();
736  }
737  //flush_rx();
738  write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) );
739 
740  #if defined (RF24_TINY) || defined (LITTLEWIRE)
741  // for 3 pins solution TX mode is only left with additonal powerDown/powerUp cycle
742  if (ce_pin == csn_pin) {
743  powerDown();
744  powerUp();
745  }
746  #endif
747  write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[0]))); // Enable RX on pipe0
748 
749  //delayMicroseconds(100);
750 
751 }
752 
753 /****************************************************************************/
754 
755 void RF24::powerDown(void)
756 {
757  ce(LOW); // Guarantee CE is low on powerDown
758  write_register(NRF_CONFIG,read_register(NRF_CONFIG) & ~_BV(PWR_UP));
759 }
760 
761 /****************************************************************************/
762 
763 //Power up now. Radio will not power down unless instructed by MCU for config changes etc.
764 void RF24::powerUp(void)
765 {
766  uint8_t cfg = read_register(NRF_CONFIG);
767 
768  // if not powered up then power up and wait for the radio to initialize
769  if (!(cfg & _BV(PWR_UP))){
770  write_register(NRF_CONFIG, cfg | _BV(PWR_UP));
771 
772  // For nRF24L01+ to go from power down mode to TX or RX mode it must first pass through stand-by mode.
773  // There must be a delay of Tpd2stby (see Table 16.) after the nRF24L01+ leaves power down mode before
774  // the CEis set high. - Tpd2stby can be up to 5ms per the 1.0 datasheet
775  delay(5);
776  }
777 }
778 
779 /******************************************************************/
780 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
781 void RF24::errNotify(){
782  #if defined (SERIAL_DEBUG) || defined (RF24_LINUX)
783  printf_P(PSTR("RF24 HARDWARE FAIL: Radio not responding, verify pin connections, wiring, etc.\r\n"));
784  #endif
785  #if defined (FAILURE_HANDLING)
786  failureDetected = 1;
787  #else
788  delay(5000);
789  #endif
790 }
791 #endif
792 /******************************************************************/
793 
794 //Similar to the previous write, clears the interrupt flags
795 bool RF24::write( const void* buf, uint8_t len, const bool multicast )
796 {
797  //Start Writing
798  startFastWrite(buf,len,multicast);
799 
800  //Wait until complete or failed
801  #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
802  uint32_t timer = millis();
803  #endif
804 
805  while( ! ( get_status() & ( _BV(TX_DS) | _BV(MAX_RT) ))) {
806  #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
807  if(millis() - timer > 95){
808  errNotify();
809  #if defined (FAILURE_HANDLING)
810  return 0;
811  #else
812  delay(100);
813  #endif
814  }
815  #endif
816  }
817 
818  ce(LOW);
819 
820  uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
821 
822  //Max retries exceeded
823  if( status & _BV(MAX_RT)){
824  flush_tx(); //Only going to be 1 packet int the FIFO at a time using this method, so just flush
825  return 0;
826  }
827  //TX OK 1 or 0
828  return 1;
829 }
830 
831 bool RF24::write( const void* buf, uint8_t len ){
832  return write(buf,len,0);
833 }
834 /****************************************************************************/
835 
836 //For general use, the interrupt flags are not important to clear
837 bool RF24::writeBlocking( const void* buf, uint8_t len, uint32_t timeout )
838 {
839  //Block until the FIFO is NOT full.
840  //Keep track of the MAX retries and set auto-retry if seeing failures
841  //This way the FIFO will fill up and allow blocking until packets go through
842  //The radio will auto-clear everything in the FIFO as long as CE remains high
843 
844  uint32_t timer = millis(); //Get the time that the payload transmission started
845 
846  while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or timeout
847 
848  if( get_status() & _BV(MAX_RT)){ //If MAX Retries have been reached
849  reUseTX(); //Set re-transmit and clear the MAX_RT interrupt flag
850  if(millis() - timer > timeout){ return 0; } //If this payload has exceeded the user-defined timeout, exit and return 0
851  }
852  #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
853  if(millis() - timer > (timeout+95) ){
854  errNotify();
855  #if defined (FAILURE_HANDLING)
856  return 0;
857  #endif
858  }
859  #endif
860 
861  }
862 
863  //Start Writing
864  startFastWrite(buf,len,0); //Write the payload if a buffer is clear
865 
866  return 1; //Return 1 to indicate successful transmission
867 }
868 
869 /****************************************************************************/
870 
872  write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag
873  spiTrans( REUSE_TX_PL );
874  ce(LOW); //Re-Transfer packet
875  ce(HIGH);
876 }
877 
878 /****************************************************************************/
879 
880 bool RF24::writeFast( const void* buf, uint8_t len, const bool multicast )
881 {
882  //Block until the FIFO is NOT full.
883  //Keep track of the MAX retries and set auto-retry if seeing failures
884  //Return 0 so the user can control the retrys and set a timer or failure counter if required
885  //The radio will auto-clear everything in the FIFO as long as CE remains high
886 
887  #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
888  uint32_t timer = millis();
889  #endif
890 
891  while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or fail
892 
893  if( get_status() & _BV(MAX_RT)){
894  //reUseTX(); //Set re-transmit
895  write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag
896  return 0; //Return 0. The previous payload has been retransmitted
897  //From the user perspective, if you get a 0, just keep trying to send the same payload
898  }
899  #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
900  if(millis() - timer > 95 ){
901  errNotify();
902  #if defined (FAILURE_HANDLING)
903  return 0;
904  #endif
905  }
906  #endif
907  }
908  //Start Writing
909  startFastWrite(buf,len,multicast);
910 
911  return 1;
912 }
913 
914 bool RF24::writeFast( const void* buf, uint8_t len ){
915  return writeFast(buf,len,0);
916 }
917 
918 /****************************************************************************/
919 
920 //Per the documentation, we want to set PTX Mode when not listening. Then all we do is write data and set CE high
921 //In this mode, if we can keep the FIFO buffers loaded, packets will transmit immediately (no 130us delay)
922 //Otherwise we enter Standby-II mode, which is still faster than standby mode
923 //Also, we remove the need to keep writing the config register over and over and delaying for 150 us each time if sending a stream of data
924 
925 void RF24::startFastWrite( const void* buf, uint8_t len, const bool multicast, bool startTx){ //TMRh20
926 
927  //write_payload( buf,len);
928  write_payload( buf, len,multicast ? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
929  if(startTx){
930  ce(HIGH);
931  }
932 
933 }
934 
935 /****************************************************************************/
936 
937 //Added the original startWrite back in so users can still use interrupts, ack payloads, etc
938 //Allows the library to pass all tests
939 void RF24::startWrite( const void* buf, uint8_t len, const bool multicast ){
940 
941  // Send the payload
942 
943  //write_payload( buf, len );
944  write_payload( buf, len,multicast? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
945  ce(HIGH);
946  #if defined(CORE_TEENSY) || !defined(ARDUINO) || defined (RF24_SPIDEV) || defined (RF24_DUE)
947  delayMicroseconds(10);
948  #endif
949  ce(LOW);
950 
951 
952 }
953 
954 /****************************************************************************/
955 
957  return read_register(FIFO_STATUS) & _BV(RX_FULL);
958 }
959 /****************************************************************************/
960 
962 
963  #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
964  uint32_t timeout = millis();
965  #endif
966  while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){
967  if( get_status() & _BV(MAX_RT)){
968  write_register(NRF_STATUS,_BV(MAX_RT) );
969  ce(LOW);
970  flush_tx(); //Non blocking, flush the data
971  return 0;
972  }
973  #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
974  if( millis() - timeout > 95){
975  errNotify();
976  #if defined (FAILURE_HANDLING)
977  return 0;
978  #endif
979  }
980  #endif
981  }
982 
983  ce(LOW); //Set STANDBY-I mode
984  return 1;
985 }
986 
987 /****************************************************************************/
988 
989 bool RF24::txStandBy(uint32_t timeout, bool startTx){
990 
991  if(startTx){
992  stopListening();
993  ce(HIGH);
994  }
995  uint32_t start = millis();
996 
997  while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){
998  if( get_status() & _BV(MAX_RT)){
999  write_register(NRF_STATUS,_BV(MAX_RT) );
1000  ce(LOW); //Set re-transmit
1001  ce(HIGH);
1002  if(millis() - start >= timeout){
1003  ce(LOW); flush_tx(); return 0;
1004  }
1005  }
1006  #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
1007  if( millis() - start > (timeout+95)){
1008  errNotify();
1009  #if defined (FAILURE_HANDLING)
1010  return 0;
1011  #endif
1012  }
1013  #endif
1014  }
1015 
1016 
1017  ce(LOW); //Set STANDBY-I mode
1018  return 1;
1019 
1020 }
1021 
1022 /****************************************************************************/
1023 
1024 void RF24::maskIRQ(bool tx, bool fail, bool rx){
1025 
1026  uint8_t config = read_register(NRF_CONFIG);
1027  /* clear the interrupt flags */
1028  config &= ~(1 << MASK_MAX_RT | 1 << MASK_TX_DS | 1 << MASK_RX_DR);
1029  /* set the specified interrupt flags */
1030  config |= fail << MASK_MAX_RT | tx << MASK_TX_DS | rx << MASK_RX_DR;
1031  write_register(NRF_CONFIG, config);
1032 }
1033 
1034 /****************************************************************************/
1035 
1037 {
1038  uint8_t result = 0;
1039 
1040  #if defined (RF24_LINUX)
1041  spi_txbuff[0] = R_RX_PL_WID;
1042  spi_rxbuff[1] = 0xff;
1043  beginTransaction();
1044  _SPI.transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, 2);
1045  result = spi_rxbuff[1];
1046  endTransaction();
1047  #else
1048  beginTransaction();
1049  _SPI.transfer( R_RX_PL_WID );
1050  result = _SPI.transfer(0xff);
1051  endTransaction();
1052  #endif
1053 
1054  if(result > 32) { flush_rx(); delay(2); return 0; }
1055  return result;
1056 }
1057 
1058 /****************************************************************************/
1059 
1061 {
1062  return available(NULL);
1063 }
1064 
1065 /****************************************************************************/
1066 
1067 bool RF24::available(uint8_t* pipe_num)
1068 {
1069  if (!( read_register(FIFO_STATUS) & _BV(RX_EMPTY) )){
1070 
1071  // If the caller wants the pipe number, include that
1072  if ( pipe_num ){
1073  uint8_t status = get_status();
1074  *pipe_num = ( status >> RX_P_NO ) & 0b111;
1075  }
1076  return 1;
1077  }
1078 
1079 
1080  return 0;
1081 
1082 
1083 }
1084 
1085 /****************************************************************************/
1086 
1087 void RF24::read( void* buf, uint8_t len ){
1088 
1089  // Fetch the payload
1090  read_payload( buf, len );
1091 
1092  //Clear the two possible interrupt flags with one command
1093  write_register(NRF_STATUS,_BV(RX_DR) | _BV(MAX_RT) | _BV(TX_DS) );
1094 
1095 }
1096 
1097 /****************************************************************************/
1098 
1099 void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready)
1100 {
1101  // Read the status & reset the status in one easy call
1102  // Or is that such a good idea?
1103  uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
1104 
1105  // Report to the user what happened
1106  tx_ok = status & _BV(TX_DS);
1107  tx_fail = status & _BV(MAX_RT);
1108  rx_ready = status & _BV(RX_DR);
1109 }
1110 
1111 /****************************************************************************/
1112 
1113 void RF24::openWritingPipe(uint64_t value)
1114 {
1115  // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
1116  // expects it LSB first too, so we're good.
1117 
1118  write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), addr_width);
1119  write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&value), addr_width);
1120 
1121 
1122  //const uint8_t max_payload_size = 32;
1123  //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size));
1124  write_register(RX_PW_P0,payload_size);
1125 }
1126 
1127 /****************************************************************************/
1128 void RF24::openWritingPipe(const uint8_t *address)
1129 {
1130  // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
1131  // expects it LSB first too, so we're good.
1132 
1133  write_register(RX_ADDR_P0,address, addr_width);
1134  write_register(TX_ADDR, address, addr_width);
1135 
1136  //const uint8_t max_payload_size = 32;
1137  //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size));
1138  write_register(RX_PW_P0,payload_size);
1139 }
1140 
1141 /****************************************************************************/
1142 static const uint8_t child_pipe[] PROGMEM =
1143 {
1145 };
1146 static const uint8_t child_payload_size[] PROGMEM =
1147 {
1149 };
1150 
1151 
1152 void RF24::openReadingPipe(uint8_t child, uint64_t address)
1153 {
1154  // If this is pipe 0, cache the address. This is needed because
1155  // openWritingPipe() will overwrite the pipe 0 address, so
1156  // startListening() will have to restore it.
1157  if (child == 0){
1158  memcpy(pipe0_reading_address,&address,addr_width);
1159  }
1160 
1161  if (child <= 6)
1162  {
1163  // For pipes 2-5, only write the LSB
1164  if ( child < 2 )
1165  write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), addr_width);
1166  else
1167  write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), 1);
1168 
1169  write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
1170 
1171  // Note it would be more efficient to set all of the bits for all open
1172  // pipes at once. However, I thought it would make the calling code
1173  // more simple to do it this way.
1174  write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
1175  }
1176 }
1177 
1178 /****************************************************************************/
1179 void RF24::setAddressWidth(uint8_t a_width){
1180 
1181  if(a_width -= 2){
1182  write_register(SETUP_AW,a_width%4);
1183  addr_width = (a_width%4) + 2;
1184  }
1185 
1186 }
1187 
1188 /****************************************************************************/
1189 
1190 void RF24::openReadingPipe(uint8_t child, const uint8_t *address)
1191 {
1192  // If this is pipe 0, cache the address. This is needed because
1193  // openWritingPipe() will overwrite the pipe 0 address, so
1194  // startListening() will have to restore it.
1195  if (child == 0){
1196  memcpy(pipe0_reading_address,address,addr_width);
1197  }
1198  if (child <= 6)
1199  {
1200  // For pipes 2-5, only write the LSB
1201  if ( child < 2 ){
1202  write_register(pgm_read_byte(&child_pipe[child]), address, addr_width);
1203  }else{
1204  write_register(pgm_read_byte(&child_pipe[child]), address, 1);
1205  }
1206  write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
1207 
1208  // Note it would be more efficient to set all of the bits for all open
1209  // pipes at once. However, I thought it would make the calling code
1210  // more simple to do it this way.
1211  write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
1212 
1213  }
1214 }
1215 
1216 /****************************************************************************/
1217 
1218 void RF24::closeReadingPipe( uint8_t pipe )
1219 {
1220  write_register(EN_RXADDR,read_register(EN_RXADDR) & ~_BV(pgm_read_byte(&child_pipe_enable[pipe])));
1221 }
1222 
1223 /****************************************************************************/
1224 
1225 void RF24::toggle_features(void)
1226 {
1227  beginTransaction();
1228  _SPI.transfer( ACTIVATE );
1229  _SPI.transfer( 0x73 );
1230  endTransaction();
1231 }
1232 
1233 /****************************************************************************/
1234 
1236 {
1237  // Enable dynamic payload throughout the system
1238 
1239  //toggle_features();
1240  write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
1241 
1242 
1243  IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
1244 
1245  // Enable dynamic payload on all pipes
1246  //
1247  // Not sure the use case of only having dynamic payload on certain
1248  // pipes, so the library does not support it.
1249  write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0));
1250 
1251  dynamic_payloads_enabled = true;
1252 }
1253 
1254 /****************************************************************************/
1255 
1257 {
1258  //
1259  // enable ack payload and dynamic payload features
1260  //
1261 
1262  //toggle_features();
1263  write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
1264 
1265  IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
1266 
1267  //
1268  // Enable dynamic payload on pipes 0 & 1
1269  //
1270 
1271  write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0));
1272  dynamic_payloads_enabled = true;
1273 }
1274 
1275 /****************************************************************************/
1276 
1278  //
1279  // enable dynamic ack features
1280  //
1281  //toggle_features();
1282  write_register(FEATURE,read_register(FEATURE) | _BV(EN_DYN_ACK) );
1283 
1284  IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
1285 
1286 
1287 }
1288 
1289 /****************************************************************************/
1290 
1291 void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
1292 {
1293  const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
1294 
1295  uint8_t data_len = rf24_min(len,32);
1296 
1297  #if defined (RF24_LINUX)
1298  beginTransaction();
1299  uint8_t * ptx = spi_txbuff;
1300  uint8_t size = data_len + 1 ; // Add register value to transmit buffer
1301  *ptx++ = W_ACK_PAYLOAD | ( pipe & 0b111 );
1302  while ( data_len-- ){
1303  *ptx++ = *current++;
1304  }
1305 
1306  _SPI.transfern( (char *) spi_txbuff, size);
1307  endTransaction();
1308  #else
1309  beginTransaction();
1310  _SPI.transfer(W_ACK_PAYLOAD | ( pipe & 0b111 ) );
1311 
1312  while ( data_len-- )
1313  _SPI.transfer(*current++);
1314  endTransaction();
1315 
1316  #endif
1317 
1318 }
1319 
1320 /****************************************************************************/
1321 
1323 {
1324  return ! (read_register(FIFO_STATUS) & _BV(RX_EMPTY));
1325 }
1326 
1327 /****************************************************************************/
1328 
1330 {
1331  return p_variant ;
1332 }
1333 
1334 /****************************************************************************/
1335 
1336 void RF24::setAutoAck(bool enable)
1337 {
1338  if ( enable )
1339  write_register(EN_AA, 0b111111);
1340  else
1341  write_register(EN_AA, 0);
1342 }
1343 
1344 /****************************************************************************/
1345 
1346 void RF24::setAutoAck( uint8_t pipe, bool enable )
1347 {
1348  if ( pipe <= 6 )
1349  {
1350  uint8_t en_aa = read_register( EN_AA ) ;
1351  if( enable )
1352  {
1353  en_aa |= _BV(pipe) ;
1354  }
1355  else
1356  {
1357  en_aa &= ~_BV(pipe) ;
1358  }
1359  write_register( EN_AA, en_aa ) ;
1360  }
1361 }
1362 
1363 /****************************************************************************/
1364 
1366 {
1367  return ( read_register(CD) & 1 );
1368 }
1369 
1370 /****************************************************************************/
1371 
1372 bool RF24::testRPD(void)
1373 {
1374  return ( read_register(RPD) & 1 ) ;
1375 }
1376 
1377 /****************************************************************************/
1378 
1379 void RF24::setPALevel(uint8_t level)
1380 {
1381 
1382  uint8_t setup = read_register(RF_SETUP) & 0b11111000;
1383 
1384  if(level > 3){ // If invalid level, go to max PA
1385  level = (RF24_PA_MAX << 1) + 1; // +1 to support the SI24R1 chip extra bit
1386  }else{
1387  level = (level << 1) + 1; // Else set level as requested
1388  }
1389 
1390 
1391  write_register( RF_SETUP, setup |= level ) ; // Write it to the chip
1392 }
1393 
1394 /****************************************************************************/
1395 
1396 uint8_t RF24::getPALevel(void)
1397 {
1398 
1399  return (read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH))) >> 1 ;
1400 }
1401 
1402 /****************************************************************************/
1403 
1405 {
1406  bool result = false;
1407  uint8_t setup = read_register(RF_SETUP) ;
1408 
1409  // HIGH and LOW '00' is 1Mbs - our default
1410  setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ;
1411 
1412  #if defined(__arm__) || defined (RF24_LINUX) || defined (__ARDUINO_X86__)
1413  txDelay=250;
1414  #else //16Mhz Arduino
1415  txDelay=85;
1416  #endif
1417  if( speed == RF24_250KBPS )
1418  {
1419  // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0
1420  // Making it '10'.
1421  setup |= _BV( RF_DR_LOW ) ;
1422  #if defined(__arm__) || defined (RF24_LINUX) || defined (__ARDUINO_X86__)
1423  txDelay=450;
1424  #else //16Mhz Arduino
1425  txDelay=155;
1426  #endif
1427  }
1428  else
1429  {
1430  // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1
1431  // Making it '01'
1432  if ( speed == RF24_2MBPS )
1433  {
1434  setup |= _BV(RF_DR_HIGH);
1435  #if defined(__arm__) || defined (RF24_LINUX) || defined (__ARDUINO_X86__)
1436  txDelay=190;
1437  #else //16Mhz Arduino
1438  txDelay=65;
1439  #endif
1440  }
1441  }
1442  write_register(RF_SETUP,setup);
1443 
1444  // Verify our result
1445  if ( read_register(RF_SETUP) == setup )
1446  {
1447  result = true;
1448  }
1449  return result;
1450 }
1451 
1452 /****************************************************************************/
1453 
1455 {
1456  rf24_datarate_e result ;
1457  uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH));
1458 
1459  // switch uses RAM (evil!)
1460  // Order matters in our case below
1461  if ( dr == _BV(RF_DR_LOW) )
1462  {
1463  // '10' = 250KBPS
1464  result = RF24_250KBPS ;
1465  }
1466  else if ( dr == _BV(RF_DR_HIGH) )
1467  {
1468  // '01' = 2MBPS
1469  result = RF24_2MBPS ;
1470  }
1471  else
1472  {
1473  // '00' = 1MBPS
1474  result = RF24_1MBPS ;
1475  }
1476  return result ;
1477 }
1478 
1479 /****************************************************************************/
1480 
1482 {
1483  uint8_t config = read_register(NRF_CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ;
1484 
1485  // switch uses RAM (evil!)
1486  if ( length == RF24_CRC_DISABLED )
1487  {
1488  // Do nothing, we turned it off above.
1489  }
1490  else if ( length == RF24_CRC_8 )
1491  {
1492  config |= _BV(EN_CRC);
1493  }
1494  else
1495  {
1496  config |= _BV(EN_CRC);
1497  config |= _BV( CRCO );
1498  }
1499  write_register( NRF_CONFIG, config ) ;
1500 }
1501 
1502 /****************************************************************************/
1503 
1505 {
1507 
1508  uint8_t config = read_register(NRF_CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ;
1509  uint8_t AA = read_register(EN_AA);
1510 
1511  if ( config & _BV(EN_CRC ) || AA)
1512  {
1513  if ( config & _BV(CRCO) )
1514  result = RF24_CRC_16;
1515  else
1516  result = RF24_CRC_8;
1517  }
1518 
1519  return result;
1520 }
1521 
1522 /****************************************************************************/
1523 
1524 void RF24::disableCRC( void )
1525 {
1526  uint8_t disable = read_register(NRF_CONFIG) & ~_BV(EN_CRC) ;
1527  write_register( NRF_CONFIG, disable ) ;
1528 }
1529 
1530 /****************************************************************************/
1531 void RF24::setRetries(uint8_t delay, uint8_t count)
1532 {
1533  write_register(SETUP_RETR,(delay&0xf)<<ARD | (count&0xf)<<ARC);
1534 }
1535 
1536 
1537 //ATTiny support code pulled in from https://github.com/jscrane/RF24
1538 
1539 #if defined(__AVR_ATtiny25__) || defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny85__)
1540 // see http://gammon.com.au/spi
1541 # define DI 0 // D0, pin 5 Data In
1542 # define DO 1 // D1, pin 6 Data Out (this is *not* MOSI)
1543 # define USCK 2 // D2, pin 7 Universal Serial Interface clock
1544 # define SS 3 // D3, pin 2 Slave Select
1545 #elif defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__)
1546 // these depend on the core used (check pins_arduino.h)
1547 // this is for jeelabs' one (based on google-code core)
1548 # define DI 4 // PA6
1549 # define DO 5 // PA5
1550 # define USCK 6 // PA4
1551 # define SS 3 // PA7
1552 #elif defined(__AVR_ATtiny2313__) || defined(__AVR_ATtiny4313__)
1553 // these depend on the core used (check pins_arduino.h)
1554 // tested with google-code core
1555 # define DI 14 // PB5
1556 # define DO 15 // PB6
1557 # define USCK 16 // PB7
1558 # define SS 13 // PB4
1559 #elif defined(__AVR_ATtiny861__)
1560 // these depend on the core used (check pins_arduino.h)
1561 // tested with google-code core
1562 # define DI 9 // PB0
1563 # define DO 8 // PB1
1564 # define USCK 7 // PB2
1565 # define SS 6 // PB3
1566 #endif
1567 
1568 #if defined(RF24_TINY)
1569 
1570 void SPIClass::begin() {
1571 
1572  pinMode(USCK, OUTPUT);
1573  pinMode(DO, OUTPUT);
1574  pinMode(DI, INPUT);
1575  USICR = _BV(USIWM0);
1576 
1577 }
1578 
1579 byte SPIClass::transfer(byte b) {
1580 
1581  USIDR = b;
1582  USISR = _BV(USIOIF);
1583  do
1584  USICR = _BV(USIWM0) | _BV(USICS1) | _BV(USICLK) | _BV(USITC);
1585  while ((USISR & _BV(USIOIF)) == 0);
1586  return USIDR;
1587 
1588 }
1589 
1590 void SPIClass::end() {}
1591 void SPIClass::setDataMode(uint8_t mode){}
1592 void SPIClass::setBitOrder(uint8_t bitOrder){}
1593 void SPIClass::setClockDivider(uint8_t rate){}
1594 
1595 
1596 #endif
#define RF_PWR_LOW
Definition: nRF24L01.h:126
#define EN_DYN_ACK
Definition: nRF24L01.h:100
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Definition: nRF24L01.h:70
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Definition: nRF24L01.h:57
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Definition: RF24.cpp:1336
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Definition: nRF24L01.h:34
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Definition: RF24.cpp:956
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Definition: RF24.h:673
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Definition: RF24.cpp:1218
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Definition: RF24.cpp:512
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Definition: RF24.cpp:1454
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Definition: RF24.cpp:437
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Definition: nRF24L01.h:84
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Definition: nRF24L01.h:125
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Definition: RF24.cpp:1372
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Definition: nRF24L01.h:91
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Definition: RF24.h:920
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Definition: nRF24L01.h:71
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Definition: spi.h:74
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Definition: RF24.cpp:939
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Definition: RF24.cpp:1531
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Definition: nRF24L01.h:31
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Definition: RF24.cpp:1524
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Definition: RF24.cpp:77
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Definition: RF24.cpp:450
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Definition: RF24.cpp:1329
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Definition: nRF24L01.h:33
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Definition: RF24.cpp:696
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RF24(uint8_t _cepin, uint8_t _cspin)
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GPIO()
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Definition: RF24.cpp:457
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rf24_datarate_e
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static const char rf24_datarate_e_str_0[] PROGMEM
Definition: RF24.cpp:466
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Definition: RF24.cpp:1504
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Definition: spi.h:70
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Definition: nRF24L01.h:93
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Definition: nRF24L01.h:58