Optimized High Speed NRF24L01+ Driver Class Documenation  V1.0
TMRh20 2014 - Optimized Fork of NRF24L01+ Driver
RF24.cpp
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1 /*
2  Copyright (C) 2011 J. Coliz <maniacbug@ymail.com>
3 
4  This program is free software; you can redistribute it and/or
5  modify it under the terms of the GNU General Public License
6  version 2 as published by the Free Software Foundation.
7  */
8 
9 #include "nRF24L01.h"
10 #include "RF24_config.h"
11 #include "RF24.h"
12 
13 /****************************************************************************/
14 
15 void RF24::csn(bool mode)
16 {
17 
18 #if defined (RF24_TINY)
19  if (ce_pin != csn_pin) {
20  digitalWrite(csn_pin,mode);
21  }
22  else {
23  if (mode == HIGH) {
24  PORTB |= (1<<PINB2); // SCK->CSN HIGH
25  delayMicroseconds(100); // allow csn to settle.
26  }
27  else {
28  PORTB &= ~(1<<PINB2); // SCK->CSN LOW
29  delayMicroseconds(11); // allow csn to settle
30  }
31  }
32  // Return, CSN toggle complete
33  return;
34 
35 #elif defined(ARDUINO) && !defined (RF24_SPI_TRANSACTIONS)
36  // Minimum ideal SPI bus speed is 2x data rate
37  // If we assume 2Mbs data rate and 16Mhz clock, a
38  // divider of 4 is the minimum we want.
39  // CLK:BUS 8Mhz:2Mhz, 16Mhz:4Mhz, or 20Mhz:5Mhz
40 
41  #if !defined (SOFTSPI)
42  _SPI.setBitOrder(MSBFIRST);
43  _SPI.setDataMode(SPI_MODE0);
44  #if !defined(F_CPU) || F_CPU < 20000000
45  _SPI.setClockDivider(SPI_CLOCK_DIV2);
46  #elif F_CPU < 40000000
47  _SPI.setClockDivider(SPI_CLOCK_DIV4);
48  #elif F_CPU < 80000000
49  _SPI.setClockDivider(SPI_CLOCK_DIV8);
50  #elif F_CPU < 160000000
51  _SPI.setClockDivider(SPI_CLOCK_DIV16);
52  #elif F_CPU < 320000000
53  _SPI.setClockDivider(SPI_CLOCK_DIV32);
54  #elif F_CPU < 640000000
55  _SPI.setClockDivider(SPI_CLOCK_DIV64);
56  #elif F_CPU < 1280000000
57  _SPI.setClockDivider(SPI_CLOCK_DIV128);
58  #else
59  #error "Unsupported CPU frequency. Please set correct SPI divider."
60  #endif
61 
62  #endif
63 #elif defined (RF24_RPi)
64  if(!mode)
65  _SPI.chipSelect(csn_pin);
66 #endif
67 
68 #if !defined (RF24_LINUX)
69  digitalWrite(csn_pin,mode);
71 #endif
72 
73 }
74 
75 /****************************************************************************/
76 
77 void RF24::ce(bool level)
78 {
79  //Allow for 3-pin use on ATTiny
80  if (ce_pin != csn_pin) digitalWrite(ce_pin,level);
81 }
82 
83 /****************************************************************************/
84 
85  inline void RF24::beginTransaction() {
86  #if defined (RF24_SPI_TRANSACTIONS)
87  _SPI.beginTransaction(SPISettings(RF24_SPI_SPEED, MSBFIRST, SPI_MODE0));
88  #endif
89  csn(LOW);
90  }
91 
92 /****************************************************************************/
93 
94  inline void RF24::endTransaction() {
95  csn(HIGH);
96  #if defined (RF24_SPI_TRANSACTIONS)
97  _SPI.endTransaction();
98  #endif
99  }
100 
101 /****************************************************************************/
102 
103 uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
104 {
105  uint8_t status;
106 
107  #if defined (RF24_LINUX)
108  beginTransaction(); //configures the spi settings for RPi, locks mutex and setting csn low
109  uint8_t * prx = spi_rxbuff;
110  uint8_t * ptx = spi_txbuff;
111  uint8_t size = len + 1; // Add register value to transmit buffer
112 
113  *ptx++ = ( R_REGISTER | ( REGISTER_MASK & reg ) );
114 
115  while (len--){ *ptx++ = RF24_NOP; } // Dummy operation, just for reading
116 
117  _SPI.transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, size);
118 
119  status = *prx++; // status is 1st byte of receive buffer
120 
121  // decrement before to skip status byte
122  while ( --size ){ *buf++ = *prx++; }
123  endTransaction(); //unlocks mutex and setting csn high
124 
125 #else
126 
128  status = _SPI.transfer( R_REGISTER | ( REGISTER_MASK & reg ) );
129  while ( len-- ){
130  *buf++ = _SPI.transfer(0xff);
131  }
132  endTransaction();
133 
134 #endif
135 
136  return status;
137 }
138 
139 /****************************************************************************/
140 
141 uint8_t RF24::read_register(uint8_t reg)
142 {
143  uint8_t result;
144 
145  #if defined (RF24_LINUX)
146 
148 
149  uint8_t * prx = spi_rxbuff;
150  uint8_t * ptx = spi_txbuff;
151  *ptx++ = ( R_REGISTER | ( REGISTER_MASK & reg ) );
152  *ptx++ = RF24_NOP ; // Dummy operation, just for reading
153 
154  _SPI.transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, 2);
155  result = *++prx; // result is 2nd byte of receive buffer
156 
157  endTransaction();
158  #else
159 
161  _SPI.transfer( R_REGISTER | ( REGISTER_MASK & reg ) );
162  result = _SPI.transfer(0xff);
163  endTransaction();
164 
165  #endif
166 
167  return result;
168 }
169 
170 /****************************************************************************/
171 
172 uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
173 {
174  uint8_t status;
175 
176  #if defined (RF24_LINUX)
178  uint8_t * prx = spi_rxbuff;
179  uint8_t * ptx = spi_txbuff;
180  uint8_t size = len + 1; // Add register value to transmit buffer
181 
182  *ptx++ = ( W_REGISTER | ( REGISTER_MASK & reg ) );
183  while ( len-- )
184  *ptx++ = *buf++;
185 
186  _SPI.transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, size);
187  status = *prx; // status is 1st byte of receive buffer
188  endTransaction();
189  #else
190 
192  status = _SPI.transfer( W_REGISTER | ( REGISTER_MASK & reg ) );
193  while ( len-- )
194  _SPI.transfer(*buf++);
195  endTransaction();
196 
197  #endif
198 
199  return status;
200 }
201 
202 /****************************************************************************/
203 
204 uint8_t RF24::write_register(uint8_t reg, uint8_t value)
205 {
206  uint8_t status;
207 
208  IF_SERIAL_DEBUG(printf_P(PSTR("write_register(%02x,%02x)\r\n"),reg,value));
209 
210  #if defined (RF24_LINUX)
212  uint8_t * prx = spi_rxbuff;
213  uint8_t * ptx = spi_txbuff;
214  *ptx++ = ( W_REGISTER | ( REGISTER_MASK & reg ) );
215  *ptx = value ;
216 
217  _SPI.transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, 2);
218  status = *prx++; // status is 1st byte of receive buffer
219  endTransaction();
220  #else
221 
223  status = _SPI.transfer( W_REGISTER | ( REGISTER_MASK & reg ) );
224  _SPI.transfer(value);
225  endTransaction();
226 
227  #endif
228 
229  return status;
230 }
231 
232 /****************************************************************************/
233 
234 uint8_t RF24::write_payload(const void* buf, uint8_t data_len, const uint8_t writeType)
235 {
236  uint8_t status;
237  const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
238 
239  data_len = rf24_min(data_len, payload_size);
240  uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
241 
242  //printf("[Writing %u bytes %u blanks]",data_len,blank_len);
243  IF_SERIAL_DEBUG( printf("[Writing %u bytes %u blanks]\n",data_len,blank_len); );
244 
245  #if defined (RF24_LINUX)
247  uint8_t * prx = spi_rxbuff;
248  uint8_t * ptx = spi_txbuff;
249  uint8_t size;
250  size = data_len + blank_len + 1 ; // Add register value to transmit buffer
251 
252  *ptx++ = writeType;
253  while ( data_len-- )
254  *ptx++ = *current++;
255  while ( blank_len-- )
256  *ptx++ = 0;
257 
258  _SPI.transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, size);
259  status = *prx; // status is 1st byte of receive buffer
260  endTransaction();
261 
262  #else
263 
265  status = _SPI.transfer( writeType );
266  while ( data_len-- ) {
267  _SPI.transfer(*current++);
268  }
269  while ( blank_len-- ) {
270  _SPI.transfer(0);
271  }
272  endTransaction();
273 
274  #endif
275 
276  return status;
277 }
278 
279 /****************************************************************************/
280 
281 uint8_t RF24::read_payload(void* buf, uint8_t data_len)
282 {
283  uint8_t status;
284  uint8_t* current = reinterpret_cast<uint8_t*>(buf);
285 
286  if(data_len > payload_size) data_len = payload_size;
287  uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
288 
289  //printf("[Reading %u bytes %u blanks]",data_len,blank_len);
290 
291  IF_SERIAL_DEBUG( printf("[Reading %u bytes %u blanks]\n",data_len,blank_len); );
292 
293  #if defined (RF24_LINUX)
295  uint8_t * prx = spi_rxbuff;
296  uint8_t * ptx = spi_txbuff;
297  uint8_t size;
298  size = data_len + blank_len + 1; // Add register value to transmit buffer
299 
300  *ptx++ = R_RX_PAYLOAD;
301  while(--size)
302  *ptx++ = RF24_NOP;
303 
304  size = data_len + blank_len + 1; // Size has been lost during while, re affect
305 
306  _SPI.transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, size);
307 
308  status = *prx++; // 1st byte is status
309 
310  if (data_len > 0) {
311  while ( --data_len ) // Decrement before to skip 1st status byte
312  *current++ = *prx++;
313 
314  *current = *prx;
315  }
316  endTransaction();
317  #else
318 
320  status = _SPI.transfer( R_RX_PAYLOAD );
321  while ( data_len-- ) {
322  *current++ = _SPI.transfer(0xFF);
323  }
324  while ( blank_len-- ) {
325  _SPI.transfer(0xff);
326  }
327  endTransaction();
328 
329  #endif
330 
331  return status;
332 }
333 
334 /****************************************************************************/
335 
336 uint8_t RF24::flush_rx(void)
337 {
338  return spiTrans( FLUSH_RX );
339 }
340 
341 /****************************************************************************/
342 
343 uint8_t RF24::flush_tx(void)
344 {
345  return spiTrans( FLUSH_TX );
346 }
347 
348 /****************************************************************************/
349 
350 uint8_t RF24::spiTrans(uint8_t cmd){
351 
352  uint8_t status;
353 
355  status = _SPI.transfer( cmd );
356  endTransaction();
357 
358  return status;
359 }
360 
361 /****************************************************************************/
362 
363 uint8_t RF24::get_status(void)
364 {
365  return spiTrans(RF24_NOP);
366 }
367 
368 /****************************************************************************/
369 #if !defined (MINIMAL)
370 void RF24::print_status(uint8_t status)
371 {
372  printf_P(PSTR("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n"),
373  status,
374  (status & _BV(RX_DR))?1:0,
375  (status & _BV(TX_DS))?1:0,
376  (status & _BV(MAX_RT))?1:0,
377  ((status >> RX_P_NO) & 0x07),
378  (status & _BV(TX_FULL))?1:0
379  );
380 }
381 
382 /****************************************************************************/
383 
384 void RF24::print_observe_tx(uint8_t value)
385 {
386  printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"),
387  value,
388  (value >> PLOS_CNT) & 0x0F,
389  (value >> ARC_CNT) & 0x0F
390  );
391 }
392 
393 /****************************************************************************/
394 
395 void RF24::print_byte_register(const char* name, uint8_t reg, uint8_t qty)
396 {
397  //char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
398  //printf_P(PSTR(PRIPSTR"\t%c ="),name,extra_tab);
399  #if defined (RF24_LINUX)
400  printf("%s\t =", name);
401  #else
402  printf_P(PSTR(PRIPSTR"\t ="),name);
403  #endif
404  while (qty--)
405  printf_P(PSTR(" 0x%02x"),read_register(reg++));
406  printf_P(PSTR("\r\n"));
407 }
408 
409 /****************************************************************************/
410 
411 void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty)
412 {
413 
414  #if defined (RF24_LINUX)
415  printf("%s\t =",name);
416  #else
417  printf_P(PSTR(PRIPSTR"\t ="),name);
418  #endif
419  while (qty--)
420  {
421  uint8_t buffer[addr_width];
422  read_register(reg++,buffer,sizeof buffer);
423 
424  printf_P(PSTR(" 0x"));
425  uint8_t* bufptr = buffer + sizeof buffer;
426  while( --bufptr >= buffer )
427  printf_P(PSTR("%02x"),*bufptr);
428  }
429 
430  printf_P(PSTR("\r\n"));
431 }
432 #endif
433 /****************************************************************************/
434 
435 RF24::RF24(uint16_t _cepin, uint16_t _cspin):
436  ce_pin(_cepin), csn_pin(_cspin), p_variant(false),
437  payload_size(32), dynamic_payloads_enabled(false), addr_width(5),csDelay(5)//,pipe0_reading_address(0)
438 {
439  pipe0_reading_address[0]=0;
440 }
441 
442 /****************************************************************************/
443 
444 #if defined (RF24_LINUX) && !defined (MRAA)//RPi constructor
445 
446 RF24::RF24(uint16_t _cepin, uint16_t _cspin, uint32_t _spi_speed):
447  ce_pin(_cepin),csn_pin(_cspin),spi_speed(_spi_speed),p_variant(false), payload_size(32), dynamic_payloads_enabled(false),addr_width(5)//,pipe0_reading_address(0)
448 {
449  pipe0_reading_address[0]=0;
450 }
451 #endif
452 
453 /****************************************************************************/
454 
455 void RF24::setChannel(uint8_t channel)
456 {
457  const uint8_t max_channel = 125;
458  write_register(RF_CH,rf24_min(channel,max_channel));
459 }
460 
462 {
463 
464  return read_register(RF_CH);
465 }
466 /****************************************************************************/
467 
468 void RF24::setPayloadSize(uint8_t size)
469 {
470  payload_size = rf24_min(size,32);
471 }
472 
473 /****************************************************************************/
474 
475 uint8_t RF24::getPayloadSize(void)
476 {
477  return payload_size;
478 }
479 
480 /****************************************************************************/
481 
482 #if !defined (MINIMAL)
483 
484 static const char rf24_datarate_e_str_0[] PROGMEM = "1MBPS";
485 static const char rf24_datarate_e_str_1[] PROGMEM = "2MBPS";
486 static const char rf24_datarate_e_str_2[] PROGMEM = "250KBPS";
487 static const char * const rf24_datarate_e_str_P[] PROGMEM = {
488  rf24_datarate_e_str_0,
489  rf24_datarate_e_str_1,
490  rf24_datarate_e_str_2,
491 };
492 static const char rf24_model_e_str_0[] PROGMEM = "nRF24L01";
493 static const char rf24_model_e_str_1[] PROGMEM = "nRF24L01+";
494 static const char * const rf24_model_e_str_P[] PROGMEM = {
495  rf24_model_e_str_0,
496  rf24_model_e_str_1,
497 };
498 static const char rf24_crclength_e_str_0[] PROGMEM = "Disabled";
499 static const char rf24_crclength_e_str_1[] PROGMEM = "8 bits";
500 static const char rf24_crclength_e_str_2[] PROGMEM = "16 bits" ;
501 static const char * const rf24_crclength_e_str_P[] PROGMEM = {
502  rf24_crclength_e_str_0,
503  rf24_crclength_e_str_1,
504  rf24_crclength_e_str_2,
505 };
506 static const char rf24_pa_dbm_e_str_0[] PROGMEM = "PA_MIN";
507 static const char rf24_pa_dbm_e_str_1[] PROGMEM = "PA_LOW";
508 static const char rf24_pa_dbm_e_str_2[] PROGMEM = "PA_HIGH";
509 static const char rf24_pa_dbm_e_str_3[] PROGMEM = "PA_MAX";
510 static const char * const rf24_pa_dbm_e_str_P[] PROGMEM = {
511  rf24_pa_dbm_e_str_0,
512  rf24_pa_dbm_e_str_1,
513  rf24_pa_dbm_e_str_2,
514  rf24_pa_dbm_e_str_3,
515 };
516 
517 #if defined (RF24_LINUX)
518 static const char rf24_csn_e_str_0[] = "CE0 (PI Hardware Driven)";
519 static const char rf24_csn_e_str_1[] = "CE1 (PI Hardware Driven)";
520 static const char rf24_csn_e_str_2[] = "CE2 (PI Hardware Driven)";
521 static const char rf24_csn_e_str_3[] = "Custom GPIO Software Driven";
522 static const char * const rf24_csn_e_str_P[] = {
523  rf24_csn_e_str_0,
524  rf24_csn_e_str_1,
525  rf24_csn_e_str_2,
526  rf24_csn_e_str_3,
527 };
528 #endif
529 
531 {
532 
533 #if defined (RF24_RPi)
534  printf("================ SPI Configuration ================\n" );
535  if (csn_pin < BCM2835_SPI_CS_NONE ){
536  printf("CSN Pin \t = %s\n",rf24_csn_e_str_P[csn_pin]);
537  }else{
538  printf("CSN Pin \t = Custom GPIO%d%s\n", csn_pin,
539  csn_pin==RPI_V2_GPIO_P1_26 ? " (CE1) Software Driven" : "" );
540  }
541  printf("CE Pin \t = Custom GPIO%d\n", ce_pin );
542  printf("Clock Speed\t = " );
543  switch (spi_speed)
544  {
545  case BCM2835_SPI_SPEED_64MHZ : printf("64 Mhz"); break ;
546  case BCM2835_SPI_SPEED_32MHZ : printf("32 Mhz"); break ;
547  case BCM2835_SPI_SPEED_16MHZ : printf("16 Mhz"); break ;
548  case BCM2835_SPI_SPEED_8MHZ : printf("8 Mhz"); break ;
549  case BCM2835_SPI_SPEED_4MHZ : printf("4 Mhz"); break ;
550  case BCM2835_SPI_SPEED_2MHZ : printf("2 Mhz"); break ;
551  case BCM2835_SPI_SPEED_1MHZ : printf("1 Mhz"); break ;
552  case BCM2835_SPI_SPEED_512KHZ: printf("512 KHz"); break ;
553  case BCM2835_SPI_SPEED_256KHZ: printf("256 KHz"); break ;
554  case BCM2835_SPI_SPEED_128KHZ: printf("128 KHz"); break ;
555  case BCM2835_SPI_SPEED_64KHZ : printf("64 KHz"); break ;
556  case BCM2835_SPI_SPEED_32KHZ : printf("32 KHz"); break ;
557  case BCM2835_SPI_SPEED_16KHZ : printf("16 KHz"); break ;
558  case BCM2835_SPI_SPEED_8KHZ : printf("8 KHz"); break ;
559  default : printf("8 Mhz"); break ;
560  }
561  printf("\n================ NRF Configuration ================\n");
562 
563 #endif //Linux
564 
565  print_status(get_status());
566 
567  print_address_register(PSTR("RX_ADDR_P0-1"),RX_ADDR_P0,2);
568  print_byte_register(PSTR("RX_ADDR_P2-5"),RX_ADDR_P2,4);
569  print_address_register(PSTR("TX_ADDR\t"),TX_ADDR);
570 
571  print_byte_register(PSTR("RX_PW_P0-6"),RX_PW_P0,6);
572  print_byte_register(PSTR("EN_AA\t"),EN_AA);
573  print_byte_register(PSTR("EN_RXADDR"),EN_RXADDR);
574  print_byte_register(PSTR("RF_CH\t"),RF_CH);
575  print_byte_register(PSTR("RF_SETUP"),RF_SETUP);
576  print_byte_register(PSTR("CONFIG\t"),NRF_CONFIG);
577  print_byte_register(PSTR("DYNPD/FEATURE"),DYNPD,2);
578 
579  printf_P(PSTR("Data Rate\t = " PRIPSTR "\r\n"),pgm_read_ptr(&rf24_datarate_e_str_P[getDataRate()]));
580  printf_P(PSTR("Model\t\t = " PRIPSTR "\r\n"),pgm_read_ptr(&rf24_model_e_str_P[isPVariant()]));
581  printf_P(PSTR("CRC Length\t = " PRIPSTR "\r\n"),pgm_read_ptr(&rf24_crclength_e_str_P[getCRCLength()]));
582  printf_P(PSTR("PA Power\t = " PRIPSTR "\r\n"), pgm_read_ptr(&rf24_pa_dbm_e_str_P[getPALevel()]));
583 
584 }
585 
586 #endif
587 /****************************************************************************/
588 
589 bool RF24::begin(void)
590 {
591 
592  uint8_t setup=0;
593 
594  #if defined (RF24_LINUX)
595 
596  #if defined (MRAA)
597  GPIO();
598  gpio.begin(ce_pin,csn_pin);
599  #endif
600 
601  #ifdef RF24_RPi
602  switch(csn_pin){ //Ensure valid hardware CS pin
603  case 0: break;
604  case 1: break;
605  // Allow BCM2835 enums for RPi
606  case 8: csn_pin = 0; break;
607  case 7: csn_pin = 1; break;
608  default: csn_pin = 0; break;
609  }
610  #endif
611 
612  _SPI.begin(csn_pin);
613 
614  pinMode(ce_pin,OUTPUT);
615  ce(LOW);
616 
617  delay(100);
618 
619  #elif defined(LITTLEWIRE)
620  pinMode(csn_pin,OUTPUT);
621  _SPI.begin();
622  csn(HIGH);
623  #elif defined(XMEGA_D3)
624  if (ce_pin != csn_pin) pinMode(ce_pin,OUTPUT);
625  _SPI.begin(csn_pin);
626  ce(LOW);
627  csn(HIGH);
628  delay(200);
629  #else
630  // Initialize pins
631  if (ce_pin != csn_pin) pinMode(ce_pin,OUTPUT);
632 
633  #if ! defined(LITTLEWIRE)
634  if (ce_pin != csn_pin)
635  #endif
636  pinMode(csn_pin,OUTPUT);
637 
638  _SPI.begin();
639  ce(LOW);
640  csn(HIGH);
641  #if defined (__ARDUINO_X86__)
642  delay(100);
643  #endif
644  #endif //Linux
645 
646  // Must allow the radio time to settle else configuration bits will not necessarily stick.
647  // This is actually only required following power up but some settling time also appears to
648  // be required after resets too. For full coverage, we'll always assume the worst.
649  // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped.
650  // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure.
651  // WARNING: Delay is based on P-variant whereby non-P *may* require different timing.
652  delay( 5 ) ;
653 
654  // Reset NRF_CONFIG and enable 16-bit CRC.
655  write_register( NRF_CONFIG, 0x0C ) ;
656 
657  // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
658  // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
659  // sizes must never be used. See documentation for a more complete explanation.
660  setRetries(5,15);
661 
662  // Reset value is MAX
663  //setPALevel( RF24_PA_MAX ) ;
664 
665  // check for connected module and if this is a p nRF24l01 variant
666  //
667  if( setDataRate( RF24_250KBPS ) )
668  {
669  p_variant = true ;
670  }
671  setup = read_register(RF_SETUP);
672  /*if( setup == 0b00001110 ) // register default for nRF24L01P
673  {
674  p_variant = true ;
675  }*/
676 
677  // Then set the data rate to the slowest (and most reliable) speed supported by all
678  // hardware.
680 
681  // Initialize CRC and request 2-byte (16bit) CRC
682  //setCRCLength( RF24_CRC_16 ) ;
683 
684  // Disable dynamic payloads, to match dynamic_payloads_enabled setting - Reset value is 0
685  toggle_features();
686  write_register(FEATURE,0 );
687  write_register(DYNPD,0);
688  dynamic_payloads_enabled = false;
689 
690  // Reset current status
691  // Notice reset and flush is the last thing we do
692  write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
693 
694  // Set up default configuration. Callers can always change it later.
695  // This channel should be universally safe and not bleed over into adjacent
696  // spectrum.
697  setChannel(76);
698 
699  // Flush buffers
700  flush_rx();
701  flush_tx();
702 
703  powerUp(); //Power up by default when begin() is called
704 
705  // Enable PTX, do not write CE high so radio will remain in standby I mode ( 130us max to transition to RX or TX instead of 1500us from powerUp )
706  // PTX should use only 22uA of power
707  write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) );
708 
709  // if setup is 0 or ff then there was no response from module
710  return ( setup != 0 && setup != 0xff );
711 }
712 
713 /****************************************************************************/
714 
716 {
717  uint8_t setup = read_register(SETUP_AW);
718  if(setup >= 1 && setup <= 3)
719  {
720  return true;
721  }
722 
723  return false;
724 }
725 
726 /****************************************************************************/
727 
729 {
730  #if !defined (RF24_TINY) && ! defined(LITTLEWIRE)
731  powerUp();
732  #endif
733  write_register(NRF_CONFIG, read_register(NRF_CONFIG) | _BV(PRIM_RX));
734  write_register(NRF_STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
735  ce(HIGH);
736  // Restore the pipe0 adddress, if exists
737  if (pipe0_reading_address[0] > 0){
738  write_register(RX_ADDR_P0, pipe0_reading_address, addr_width);
739  }else{
740  closeReadingPipe(0);
741  }
742 
743  // Flush buffers
744  //flush_rx();
745  if(read_register(FEATURE) & _BV(EN_ACK_PAY)){
746  flush_tx();
747  }
748 
749  // Go!
750  //delayMicroseconds(100);
751 }
752 
753 /****************************************************************************/
754 static const uint8_t child_pipe_enable[] PROGMEM =
755 {
757 };
758 
760 {
761  ce(LOW);
762 
764 
765  if(read_register(FEATURE) & _BV(EN_ACK_PAY)){
766  delayMicroseconds(txDelay); //200
767  flush_tx();
768  }
769  //flush_rx();
770  write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) );
771 
772  #if defined (RF24_TINY) || defined (LITTLEWIRE)
773  // for 3 pins solution TX mode is only left with additonal powerDown/powerUp cycle
774  if (ce_pin == csn_pin) {
775  powerDown();
776  powerUp();
777  }
778  #endif
779  write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[0]))); // Enable RX on pipe0
780 
781  //delayMicroseconds(100);
782 
783 }
784 
785 /****************************************************************************/
786 
787 void RF24::powerDown(void)
788 {
789  ce(LOW); // Guarantee CE is low on powerDown
790  write_register(NRF_CONFIG,read_register(NRF_CONFIG) & ~_BV(PWR_UP));
791 }
792 
793 /****************************************************************************/
794 
795 //Power up now. Radio will not power down unless instructed by MCU for config changes etc.
796 void RF24::powerUp(void)
797 {
798  uint8_t cfg = read_register(NRF_CONFIG);
799 
800  // if not powered up then power up and wait for the radio to initialize
801  if (!(cfg & _BV(PWR_UP))){
802  write_register(NRF_CONFIG, cfg | _BV(PWR_UP));
803 
804  // For nRF24L01+ to go from power down mode to TX or RX mode it must first pass through stand-by mode.
805  // There must be a delay of Tpd2stby (see Table 16.) after the nRF24L01+ leaves power down mode before
806  // the CEis set high. - Tpd2stby can be up to 5ms per the 1.0 datasheet
807  delay(5);
808  }
809 }
810 
811 /******************************************************************/
812 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
813 void RF24::errNotify(){
814  #if defined (SERIAL_DEBUG) || defined (RF24_LINUX)
815  printf_P(PSTR("RF24 HARDWARE FAIL: Radio not responding, verify pin connections, wiring, etc.\r\n"));
816  #endif
817  #if defined (FAILURE_HANDLING)
818  failureDetected = 1;
819  #else
820  delay(5000);
821  #endif
822 }
823 #endif
824 /******************************************************************/
825 
826 //Similar to the previous write, clears the interrupt flags
827 bool RF24::write( const void* buf, uint8_t len, const bool multicast )
828 {
829  //Start Writing
830  startFastWrite(buf,len,multicast);
831 
832  //Wait until complete or failed
833  #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
834  uint32_t timer = millis();
835  #endif
836 
837  while( ! ( get_status() & ( _BV(TX_DS) | _BV(MAX_RT) ))) {
838  #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
839  if(millis() - timer > 95){
840  errNotify();
841  #if defined (FAILURE_HANDLING)
842  return 0;
843  #else
844  delay(100);
845  #endif
846  }
847  #endif
848  }
849 
850  ce(LOW);
851 
852  uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
853 
854  //Max retries exceeded
855  if( status & _BV(MAX_RT)){
856  flush_tx(); //Only going to be 1 packet int the FIFO at a time using this method, so just flush
857  return 0;
858  }
859  //TX OK 1 or 0
860  return 1;
861 }
862 
863 bool RF24::write( const void* buf, uint8_t len ){
864  return write(buf,len,0);
865 }
866 /****************************************************************************/
867 
868 //For general use, the interrupt flags are not important to clear
869 bool RF24::writeBlocking( const void* buf, uint8_t len, uint32_t timeout )
870 {
871  //Block until the FIFO is NOT full.
872  //Keep track of the MAX retries and set auto-retry if seeing failures
873  //This way the FIFO will fill up and allow blocking until packets go through
874  //The radio will auto-clear everything in the FIFO as long as CE remains high
875 
876  uint32_t timer = millis(); //Get the time that the payload transmission started
877 
878  while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or timeout
879 
880  if( get_status() & _BV(MAX_RT)){ //If MAX Retries have been reached
881  reUseTX(); //Set re-transmit and clear the MAX_RT interrupt flag
882  if(millis() - timer > timeout){ return 0; } //If this payload has exceeded the user-defined timeout, exit and return 0
883  }
884  #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
885  if(millis() - timer > (timeout+95) ){
886  errNotify();
887  #if defined (FAILURE_HANDLING)
888  return 0;
889  #endif
890  }
891  #endif
892 
893  }
894 
895  //Start Writing
896  startFastWrite(buf,len,0); //Write the payload if a buffer is clear
897 
898  return 1; //Return 1 to indicate successful transmission
899 }
900 
901 /****************************************************************************/
902 
904  write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag
905  spiTrans( REUSE_TX_PL );
906  ce(LOW); //Re-Transfer packet
907  ce(HIGH);
908 }
909 
910 /****************************************************************************/
911 
912 bool RF24::writeFast( const void* buf, uint8_t len, const bool multicast )
913 {
914  //Block until the FIFO is NOT full.
915  //Keep track of the MAX retries and set auto-retry if seeing failures
916  //Return 0 so the user can control the retrys and set a timer or failure counter if required
917  //The radio will auto-clear everything in the FIFO as long as CE remains high
918 
919  #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
920  uint32_t timer = millis();
921  #endif
922 
923  while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or fail
924 
925  if( get_status() & _BV(MAX_RT)){
926  //reUseTX(); //Set re-transmit
927  write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag
928  return 0; //Return 0. The previous payload has been retransmitted
929  //From the user perspective, if you get a 0, just keep trying to send the same payload
930  }
931  #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
932  if(millis() - timer > 95 ){
933  errNotify();
934  #if defined (FAILURE_HANDLING)
935  return 0;
936  #endif
937  }
938  #endif
939  }
940  //Start Writing
941  startFastWrite(buf,len,multicast);
942 
943  return 1;
944 }
945 
946 bool RF24::writeFast( const void* buf, uint8_t len ){
947  return writeFast(buf,len,0);
948 }
949 
950 /****************************************************************************/
951 
952 //Per the documentation, we want to set PTX Mode when not listening. Then all we do is write data and set CE high
953 //In this mode, if we can keep the FIFO buffers loaded, packets will transmit immediately (no 130us delay)
954 //Otherwise we enter Standby-II mode, which is still faster than standby mode
955 //Also, we remove the need to keep writing the config register over and over and delaying for 150 us each time if sending a stream of data
956 
957 void RF24::startFastWrite( const void* buf, uint8_t len, const bool multicast, bool startTx){ //TMRh20
958 
959  //write_payload( buf,len);
960  write_payload( buf, len,multicast ? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
961  if(startTx){
962  ce(HIGH);
963  }
964 
965 }
966 
967 /****************************************************************************/
968 
969 //Added the original startWrite back in so users can still use interrupts, ack payloads, etc
970 //Allows the library to pass all tests
971 void RF24::startWrite( const void* buf, uint8_t len, const bool multicast ){
972 
973  // Send the payload
974 
975  //write_payload( buf, len );
976  write_payload( buf, len,multicast? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
977  ce(HIGH);
978  #if !defined(F_CPU) || F_CPU > 20000000
979  delayMicroseconds(10);
980  #endif
981  ce(LOW);
982 
983 
984 }
985 
986 /****************************************************************************/
987 
989  return read_register(FIFO_STATUS) & _BV(RX_FULL);
990 }
991 /****************************************************************************/
992 
994 
995  #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
996  uint32_t timeout = millis();
997  #endif
998  while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){
999  if( get_status() & _BV(MAX_RT)){
1000  write_register(NRF_STATUS,_BV(MAX_RT) );
1001  ce(LOW);
1002  flush_tx(); //Non blocking, flush the data
1003  return 0;
1004  }
1005  #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
1006  if( millis() - timeout > 95){
1007  errNotify();
1008  #if defined (FAILURE_HANDLING)
1009  return 0;
1010  #endif
1011  }
1012  #endif
1013  }
1014 
1015  ce(LOW); //Set STANDBY-I mode
1016  return 1;
1017 }
1018 
1019 /****************************************************************************/
1020 
1021 bool RF24::txStandBy(uint32_t timeout, bool startTx){
1022 
1023  if(startTx){
1024  stopListening();
1025  ce(HIGH);
1026  }
1027  uint32_t start = millis();
1028 
1029  while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){
1030  if( get_status() & _BV(MAX_RT)){
1031  write_register(NRF_STATUS,_BV(MAX_RT) );
1032  ce(LOW); //Set re-transmit
1033  ce(HIGH);
1034  if(millis() - start >= timeout){
1035  ce(LOW); flush_tx(); return 0;
1036  }
1037  }
1038  #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
1039  if( millis() - start > (timeout+95)){
1040  errNotify();
1041  #if defined (FAILURE_HANDLING)
1042  return 0;
1043  #endif
1044  }
1045  #endif
1046  }
1047 
1048 
1049  ce(LOW); //Set STANDBY-I mode
1050  return 1;
1051 
1052 }
1053 
1054 /****************************************************************************/
1055 
1056 void RF24::maskIRQ(bool tx, bool fail, bool rx){
1057 
1058  uint8_t config = read_register(NRF_CONFIG);
1059  /* clear the interrupt flags */
1060  config &= ~(1 << MASK_MAX_RT | 1 << MASK_TX_DS | 1 << MASK_RX_DR);
1061  /* set the specified interrupt flags */
1062  config |= fail << MASK_MAX_RT | tx << MASK_TX_DS | rx << MASK_RX_DR;
1063  write_register(NRF_CONFIG, config);
1064 }
1065 
1066 /****************************************************************************/
1067 
1069 {
1070  uint8_t result = 0;
1071 
1072  #if defined (RF24_LINUX)
1073  spi_txbuff[0] = R_RX_PL_WID;
1074  spi_rxbuff[1] = 0xff;
1075  beginTransaction();
1076  _SPI.transfernb( (char *) spi_txbuff, (char *) spi_rxbuff, 2);
1077  result = spi_rxbuff[1];
1078  endTransaction();
1079  #else
1080  beginTransaction();
1081  _SPI.transfer( R_RX_PL_WID );
1082  result = _SPI.transfer(0xff);
1083  endTransaction();
1084  #endif
1085 
1086  if(result > 32) { flush_rx(); delay(2); return 0; }
1087  return result;
1088 }
1089 
1090 /****************************************************************************/
1091 
1093 {
1094  return available(NULL);
1095 }
1096 
1097 /****************************************************************************/
1098 
1099 bool RF24::available(uint8_t* pipe_num)
1100 {
1101  if (!( read_register(FIFO_STATUS) & _BV(RX_EMPTY) )){
1102 
1103  // If the caller wants the pipe number, include that
1104  if ( pipe_num ){
1105  uint8_t status = get_status();
1106  *pipe_num = ( status >> RX_P_NO ) & 0x07;
1107  }
1108  return 1;
1109  }
1110 
1111 
1112  return 0;
1113 
1114 
1115 }
1116 
1117 /****************************************************************************/
1118 
1119 void RF24::read( void* buf, uint8_t len ){
1120 
1121  // Fetch the payload
1122  read_payload( buf, len );
1123 
1124  //Clear the two possible interrupt flags with one command
1125  write_register(NRF_STATUS,_BV(RX_DR) | _BV(MAX_RT) | _BV(TX_DS) );
1126 
1127 }
1128 
1129 /****************************************************************************/
1130 
1131 void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready)
1132 {
1133  // Read the status & reset the status in one easy call
1134  // Or is that such a good idea?
1135  uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
1136 
1137  // Report to the user what happened
1138  tx_ok = status & _BV(TX_DS);
1139  tx_fail = status & _BV(MAX_RT);
1140  rx_ready = status & _BV(RX_DR);
1141 }
1142 
1143 /****************************************************************************/
1144 
1145 void RF24::openWritingPipe(uint64_t value)
1146 {
1147  // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
1148  // expects it LSB first too, so we're good.
1149 
1150  write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), addr_width);
1151  write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&value), addr_width);
1152 
1153 
1154  //const uint8_t max_payload_size = 32;
1155  //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size));
1156  write_register(RX_PW_P0,payload_size);
1157 }
1158 
1159 /****************************************************************************/
1160 void RF24::openWritingPipe(const uint8_t *address)
1161 {
1162  // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
1163  // expects it LSB first too, so we're good.
1164 
1165  write_register(RX_ADDR_P0,address, addr_width);
1166  write_register(TX_ADDR, address, addr_width);
1167 
1168  //const uint8_t max_payload_size = 32;
1169  //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size));
1170  write_register(RX_PW_P0,payload_size);
1171 }
1172 
1173 /****************************************************************************/
1174 static const uint8_t child_pipe[] PROGMEM =
1175 {
1177 };
1178 static const uint8_t child_payload_size[] PROGMEM =
1179 {
1181 };
1182 
1183 
1184 void RF24::openReadingPipe(uint8_t child, uint64_t address)
1185 {
1186  // If this is pipe 0, cache the address. This is needed because
1187  // openWritingPipe() will overwrite the pipe 0 address, so
1188  // startListening() will have to restore it.
1189  if (child == 0){
1190  memcpy(pipe0_reading_address,&address,addr_width);
1191  }
1192 
1193  if (child <= 6)
1194  {
1195  // For pipes 2-5, only write the LSB
1196  if ( child < 2 )
1197  write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), addr_width);
1198  else
1199  write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), 1);
1200 
1201  write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
1202 
1203  // Note it would be more efficient to set all of the bits for all open
1204  // pipes at once. However, I thought it would make the calling code
1205  // more simple to do it this way.
1206  write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
1207  }
1208 }
1209 
1210 /****************************************************************************/
1211 void RF24::setAddressWidth(uint8_t a_width){
1212 
1213  if(a_width -= 2){
1214  write_register(SETUP_AW,a_width%4);
1215  addr_width = (a_width%4) + 2;
1216  }else{
1217  write_register(SETUP_AW,0);
1218  addr_width = 2;
1219  }
1220 
1221 }
1222 
1223 /****************************************************************************/
1224 
1225 void RF24::openReadingPipe(uint8_t child, const uint8_t *address)
1226 {
1227  // If this is pipe 0, cache the address. This is needed because
1228  // openWritingPipe() will overwrite the pipe 0 address, so
1229  // startListening() will have to restore it.
1230  if (child == 0){
1231  memcpy(pipe0_reading_address,address,addr_width);
1232  }
1233  if (child <= 6)
1234  {
1235  // For pipes 2-5, only write the LSB
1236  if ( child < 2 ){
1237  write_register(pgm_read_byte(&child_pipe[child]), address, addr_width);
1238  }else{
1239  write_register(pgm_read_byte(&child_pipe[child]), address, 1);
1240  }
1241  write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
1242 
1243  // Note it would be more efficient to set all of the bits for all open
1244  // pipes at once. However, I thought it would make the calling code
1245  // more simple to do it this way.
1246  write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
1247 
1248  }
1249 }
1250 
1251 /****************************************************************************/
1252 
1253 void RF24::closeReadingPipe( uint8_t pipe )
1254 {
1255  write_register(EN_RXADDR,read_register(EN_RXADDR) & ~_BV(pgm_read_byte(&child_pipe_enable[pipe])));
1256 }
1257 
1258 /****************************************************************************/
1259 
1260 void RF24::toggle_features(void)
1261 {
1262  beginTransaction();
1263  _SPI.transfer( ACTIVATE );
1264  _SPI.transfer( 0x73 );
1265  endTransaction();
1266 }
1267 
1268 /****************************************************************************/
1269 
1271 {
1272  // Enable dynamic payload throughout the system
1273 
1274  //toggle_features();
1275  write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
1276 
1277 
1278  IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
1279 
1280  // Enable dynamic payload on all pipes
1281  //
1282  // Not sure the use case of only having dynamic payload on certain
1283  // pipes, so the library does not support it.
1284  write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0));
1285 
1286  dynamic_payloads_enabled = true;
1287 }
1288 
1289 /****************************************************************************/
1291 {
1292  // Disables dynamic payload throughout the system. Also disables Ack Payloads
1293 
1294  //toggle_features();
1295  write_register(FEATURE, 0);
1296 
1297 
1298  IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
1299 
1300  // Disable dynamic payload on all pipes
1301  //
1302  // Not sure the use case of only having dynamic payload on certain
1303  // pipes, so the library does not support it.
1304  write_register(DYNPD, 0);
1305 
1306  dynamic_payloads_enabled = false;
1307 }
1308 
1309 /****************************************************************************/
1310 
1312 {
1313  //
1314  // enable ack payload and dynamic payload features
1315  //
1316 
1317  //toggle_features();
1318  write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
1319 
1320  IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
1321 
1322  //
1323  // Enable dynamic payload on pipes 0 & 1
1324  //
1325 
1326  write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0));
1327  dynamic_payloads_enabled = true;
1328 }
1329 
1330 /****************************************************************************/
1331 
1333  //
1334  // enable dynamic ack features
1335  //
1336  //toggle_features();
1337  write_register(FEATURE,read_register(FEATURE) | _BV(EN_DYN_ACK) );
1338 
1339  IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
1340 
1341 
1342 }
1343 
1344 /****************************************************************************/
1345 
1346 void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
1347 {
1348  const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
1349 
1350  uint8_t data_len = rf24_min(len,32);
1351 
1352  #if defined (RF24_LINUX)
1353  beginTransaction();
1354  uint8_t * ptx = spi_txbuff;
1355  uint8_t size = data_len + 1 ; // Add register value to transmit buffer
1356  *ptx++ = W_ACK_PAYLOAD | ( pipe & 0x07 );
1357  while ( data_len-- ){
1358  *ptx++ = *current++;
1359  }
1360 
1361  _SPI.transfern( (char *) spi_txbuff, size);
1362  endTransaction();
1363  #else
1364  beginTransaction();
1365  _SPI.transfer(W_ACK_PAYLOAD | ( pipe & 0x07 ) );
1366 
1367  while ( data_len-- )
1368  _SPI.transfer(*current++);
1369  endTransaction();
1370 
1371  #endif
1372 
1373 }
1374 
1375 /****************************************************************************/
1376 
1378 {
1379  return ! (read_register(FIFO_STATUS) & _BV(RX_EMPTY));
1380 }
1381 
1382 /****************************************************************************/
1383 
1385 {
1386  return p_variant ;
1387 }
1388 
1389 /****************************************************************************/
1390 
1391 void RF24::setAutoAck(bool enable)
1392 {
1393  if ( enable )
1394  write_register(EN_AA, 0x3F);
1395  else
1396  write_register(EN_AA, 0);
1397 }
1398 
1399 /****************************************************************************/
1400 
1401 void RF24::setAutoAck( uint8_t pipe, bool enable )
1402 {
1403  if ( pipe <= 6 )
1404  {
1405  uint8_t en_aa = read_register( EN_AA ) ;
1406  if( enable )
1407  {
1408  en_aa |= _BV(pipe) ;
1409  }
1410  else
1411  {
1412  en_aa &= ~_BV(pipe) ;
1413  }
1414  write_register( EN_AA, en_aa ) ;
1415  }
1416 }
1417 
1418 /****************************************************************************/
1419 
1421 {
1422  return ( read_register(CD) & 1 );
1423 }
1424 
1425 /****************************************************************************/
1426 
1427 bool RF24::testRPD(void)
1428 {
1429  return ( read_register(RPD) & 1 ) ;
1430 }
1431 
1432 /****************************************************************************/
1433 
1434 void RF24::setPALevel(uint8_t level)
1435 {
1436 
1437  uint8_t setup = read_register(RF_SETUP) & 0xF8;
1438 
1439  if(level > 3){ // If invalid level, go to max PA
1440  level = (RF24_PA_MAX << 1) + 1; // +1 to support the SI24R1 chip extra bit
1441  }else{
1442  level = (level << 1) + 1; // Else set level as requested
1443  }
1444 
1445 
1446  write_register( RF_SETUP, setup |= level ) ; // Write it to the chip
1447 }
1448 
1449 /****************************************************************************/
1450 
1451 uint8_t RF24::getPALevel(void)
1452 {
1453 
1454  return (read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH))) >> 1 ;
1455 }
1456 
1457 /****************************************************************************/
1458 
1460 {
1461  bool result = false;
1462  uint8_t setup = read_register(RF_SETUP) ;
1463 
1464  // HIGH and LOW '00' is 1Mbs - our default
1465  setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ;
1466 
1467  #if !defined(F_CPU) || F_CPU > 20000000
1468  txDelay=250;
1469  #else //16Mhz Arduino
1470  txDelay=85;
1471  #endif
1472  if( speed == RF24_250KBPS )
1473  {
1474  // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0
1475  // Making it '10'.
1476  setup |= _BV( RF_DR_LOW ) ;
1477  #if !defined(F_CPU) || F_CPU > 20000000
1478  txDelay=450;
1479  #else //16Mhz Arduino
1480  txDelay=155;
1481  #endif
1482  }
1483  else
1484  {
1485  // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1
1486  // Making it '01'
1487  if ( speed == RF24_2MBPS )
1488  {
1489  setup |= _BV(RF_DR_HIGH);
1490  #if !defined(F_CPU) || F_CPU > 20000000
1491  txDelay=190;
1492  #else //16Mhz Arduino
1493  txDelay=65;
1494  #endif
1495  }
1496  }
1497  write_register(RF_SETUP,setup);
1498 
1499  // Verify our result
1500  if ( read_register(RF_SETUP) == setup )
1501  {
1502  result = true;
1503  }
1504  return result;
1505 }
1506 
1507 /****************************************************************************/
1508 
1510 {
1511  rf24_datarate_e result ;
1512  uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH));
1513 
1514  // switch uses RAM (evil!)
1515  // Order matters in our case below
1516  if ( dr == _BV(RF_DR_LOW) )
1517  {
1518  // '10' = 250KBPS
1519  result = RF24_250KBPS ;
1520  }
1521  else if ( dr == _BV(RF_DR_HIGH) )
1522  {
1523  // '01' = 2MBPS
1524  result = RF24_2MBPS ;
1525  }
1526  else
1527  {
1528  // '00' = 1MBPS
1529  result = RF24_1MBPS ;
1530  }
1531  return result ;
1532 }
1533 
1534 /****************************************************************************/
1535 
1537 {
1538  uint8_t config = read_register(NRF_CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ;
1539 
1540  // switch uses RAM (evil!)
1541  if ( length == RF24_CRC_DISABLED )
1542  {
1543  // Do nothing, we turned it off above.
1544  }
1545  else if ( length == RF24_CRC_8 )
1546  {
1547  config |= _BV(EN_CRC);
1548  }
1549  else
1550  {
1551  config |= _BV(EN_CRC);
1552  config |= _BV( CRCO );
1553  }
1554  write_register( NRF_CONFIG, config ) ;
1555 }
1556 
1557 /****************************************************************************/
1558 
1560 {
1562 
1563  uint8_t config = read_register(NRF_CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ;
1564  uint8_t AA = read_register(EN_AA);
1565 
1566  if ( config & _BV(EN_CRC ) || AA)
1567  {
1568  if ( config & _BV(CRCO) )
1569  result = RF24_CRC_16;
1570  else
1571  result = RF24_CRC_8;
1572  }
1573 
1574  return result;
1575 }
1576 
1577 /****************************************************************************/
1578 
1579 void RF24::disableCRC( void )
1580 {
1581  uint8_t disable = read_register(NRF_CONFIG) & ~_BV(EN_CRC) ;
1582  write_register( NRF_CONFIG, disable ) ;
1583 }
1584 
1585 /****************************************************************************/
1586 void RF24::setRetries(uint8_t delay, uint8_t count)
1587 {
1588  write_register(SETUP_RETR,(delay&0xf)<<ARD | (count&0xf)<<ARC);
1589 }
1590 
1591 
1592 //ATTiny support code pulled in from https://github.com/jscrane/RF24
1593 
1594 #if defined(__AVR_ATtiny25__) || defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny85__)
1595 // see http://gammon.com.au/spi
1596 # define DI 0 // D0, pin 5 Data In
1597 # define DO 1 // D1, pin 6 Data Out (this is *not* MOSI)
1598 # define USCK 2 // D2, pin 7 Universal Serial Interface clock
1599 # define SS 3 // D3, pin 2 Slave Select
1600 #elif defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__)
1601 // these depend on the core used (check pins_arduino.h)
1602 // this is for jeelabs' one (based on google-code core)
1603 # define DI 4 // PA6
1604 # define DO 5 // PA5
1605 # define USCK 6 // PA4
1606 # define SS 3 // PA7
1607 #elif defined(__AVR_ATtiny2313__) || defined(__AVR_ATtiny4313__)
1608 // these depend on the core used (check pins_arduino.h)
1609 // tested with google-code core
1610 # define DI 14 // PB5
1611 # define DO 15 // PB6
1612 # define USCK 16 // PB7
1613 # define SS 13 // PB4
1614 #elif defined(__AVR_ATtiny861__)
1615 // these depend on the core used (check pins_arduino.h)
1616 // tested with google-code core
1617 # define DI 9 // PB0
1618 # define DO 8 // PB1
1619 # define USCK 7 // PB2
1620 # define SS 6 // PB3
1621 #endif
1622 
1623 #if defined(RF24_TINY)
1624 
1625 void SPIClass::begin() {
1626 
1627  pinMode(USCK, OUTPUT);
1628  pinMode(DO, OUTPUT);
1629  pinMode(DI, INPUT);
1630  USICR = _BV(USIWM0);
1631 
1632 }
1633 
1634 byte SPIClass::transfer(byte b) {
1635 
1636  USIDR = b;
1637  USISR = _BV(USIOIF);
1638  do
1639  USICR = _BV(USIWM0) | _BV(USICS1) | _BV(USICLK) | _BV(USITC);
1640  while ((USISR & _BV(USIOIF)) == 0);
1641  return USIDR;
1642 
1643 }
1644 
1645 void SPIClass::end() {}
1646 void SPIClass::setDataMode(uint8_t mode){}
1647 void SPIClass::setBitOrder(uint8_t bitOrder){}
1648 void SPIClass::setClockDivider(uint8_t rate){}
1649 
1650 
1651 #endif
#define RF_PWR_LOW
Definition: nRF24L01.h:126
#define EN_DYN_ACK
Definition: nRF24L01.h:100
#define ERX_P3
Definition: nRF24L01.h:70
#define MASK_MAX_RT
Definition: nRF24L01.h:57
void setAutoAck(bool enable)
Definition: RF24.cpp:1391
#define NRF_STATUS
Definition: nRF24L01.h:34
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Definition: RF24.cpp:988
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Definition: RF24.h:687
void closeReadingPipe(uint8_t pipe)
Definition: RF24.cpp:1253
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Definition: RF24.cpp:530
rf24_datarate_e getDataRate(void)
Definition: RF24.cpp:1509
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Definition: nRF24L01.h:39
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Definition: nRF24L01.h:41
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Definition: RF24.cpp:455
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Definition: nRF24L01.h:92
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Definition: nRF24L01.h:36
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Definition: nRF24L01.h:83
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Definition: RF24.cpp:869
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Definition: nRF24L01.h:107
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Definition: nRF24L01.h:84
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Definition: nRF24L01.h:125
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Definition: RF24.cpp:1290
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Definition: RF24.cpp:1427
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Definition: RF24.cpp:1211
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Definition: nRF24L01.h:91
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Definition: RF24.h:945
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Definition: nRF24L01.h:108
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Definition: nRF24L01.h:71
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Definition: spi.h:74
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Definition: RF24.cpp:971
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Definition: RF24.cpp:1586
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Definition: nRF24L01.h:31
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Definition: RF24.cpp:1579
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Definition: RF24.cpp:94
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Definition: RF24.cpp:715
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Definition: RF24.cpp:343
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Definition: RF24.cpp:85
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RF24(uint16_t _cepin, uint16_t _cspin)
Definition: RF24.cpp:435
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Definition: RF24.cpp:468
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Definition: RF24.cpp:1420
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Definition: nRF24L01.h:46
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Definition: RF24.cpp:796
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Definition: RF24.cpp:1384
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#define RF_SETUP
Definition: nRF24L01.h:33
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Definition: nRF24L01.h:59
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Definition: nRF24L01.h:42
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Definition: nRF24L01.h:38
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Definition: RF24.cpp:728
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Definition: nRF24L01.h:106
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Definition: nRF24L01.h:109
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GPIO()
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Definition: RF24.cpp:1459
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Definition: nRF24L01.h:104
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Definition: nRF24L01.h:127
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Definition: RF24.cpp:475
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Definition: RF24.cpp:1332
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Definition: RF24.h:45
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Definition: nRF24L01.h:45
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Definition: nRF24L01.h:69
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Definition: nRF24L01.h:61
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rf24_datarate_e
Definition: RF24.h:38
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Definition: nRF24L01.h:51
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Definition: nRF24L01.h:73
void writeAckPayload(uint8_t pipe, const void *buf, uint8_t len)
Definition: RF24.cpp:1346
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Definition: RF24.cpp:461
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Definition: nRF24L01.h:75
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Definition: RF24.cpp:1119
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Definition: nRF24L01.h:49
#define _SPI
static const char rf24_datarate_e_str_0[] PROGMEM
Definition: RF24.cpp:484
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Definition: RF24.cpp:1559
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Definition: spi.h:70
#define pinMode(pin, direction)
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Definition: nRF24L01.h:113
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Definition: nRF24L01.h:93
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Definition: nRF24L01.h:82
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Definition: nRF24L01.h:58