Optimized High Speed NRF24L01+ Driver Class Documenation  V1.0
TMRh20 2014 - Optimized Fork of NRF24L01+ Driver
nRF24L01.h
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1 /*
2  Copyright (c) 2007 Stefan Engelke <mbox@stefanengelke.de>
3  Portions Copyright (C) 2011 Greg Copeland
4 
5  Permission is hereby granted, free of charge, to any person
6  obtaining a copy of this software and associated documentation
7  files (the "Software"), to deal in the Software without
8  restriction, including without limitation the rights to use, copy,
9  modify, merge, publish, distribute, sublicense, and/or sell copies
10  of the Software, and to permit persons to whom the Software is
11  furnished to do so, subject to the following conditions:
12 
13  The above copyright notice and this permission notice shall be
14  included in all copies or substantial portions of the Software.
15 
16  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19  NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
20  HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
21  WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23  DEALINGS IN THE SOFTWARE.
24 */
25 
26 /* Memory Map */
27 #define NRF_CONFIG 0x00
28 #define EN_AA 0x01
29 #define EN_RXADDR 0x02
30 #define SETUP_AW 0x03
31 #define SETUP_RETR 0x04
32 #define RF_CH 0x05
33 #define RF_SETUP 0x06
34 #define NRF_STATUS 0x07
35 #define OBSERVE_TX 0x08
36 #define CD 0x09
37 #define RX_ADDR_P0 0x0A
38 #define RX_ADDR_P1 0x0B
39 #define RX_ADDR_P2 0x0C
40 #define RX_ADDR_P3 0x0D
41 #define RX_ADDR_P4 0x0E
42 #define RX_ADDR_P5 0x0F
43 #define TX_ADDR 0x10
44 #define RX_PW_P0 0x11
45 #define RX_PW_P1 0x12
46 #define RX_PW_P2 0x13
47 #define RX_PW_P3 0x14
48 #define RX_PW_P4 0x15
49 #define RX_PW_P5 0x16
50 #define FIFO_STATUS 0x17
51 #define DYNPD 0x1C
52 #define FEATURE 0x1D
53 
54 /* Bit Mnemonics */
55 #define MASK_RX_DR 6
56 #define MASK_TX_DS 5
57 #define MASK_MAX_RT 4
58 #define EN_CRC 3
59 #define CRCO 2
60 #define PWR_UP 1
61 #define PRIM_RX 0
62 #define ENAA_P5 5
63 #define ENAA_P4 4
64 #define ENAA_P3 3
65 #define ENAA_P2 2
66 #define ENAA_P1 1
67 #define ENAA_P0 0
68 #define ERX_P5 5
69 #define ERX_P4 4
70 #define ERX_P3 3
71 #define ERX_P2 2
72 #define ERX_P1 1
73 #define ERX_P0 0
74 #define AW 0
75 #define ARD 4
76 #define ARC 0
77 #define PLL_LOCK 4
78 #define RF_DR 3
79 #define RF_PWR 6
80 #define RX_DR 6
81 #define TX_DS 5
82 #define MAX_RT 4
83 #define RX_P_NO 1
84 #define TX_FULL 0
85 #define PLOS_CNT 4
86 #define ARC_CNT 0
87 #define TX_REUSE 6
88 #define FIFO_FULL 5
89 #define TX_EMPTY 4
90 #define RX_FULL 1
91 #define RX_EMPTY 0
92 #define DPL_P5 5
93 #define DPL_P4 4
94 #define DPL_P3 3
95 #define DPL_P2 2
96 #define DPL_P1 1
97 #define DPL_P0 0
98 #define EN_DPL 2
99 #define EN_ACK_PAY 1
100 #define EN_DYN_ACK 0
101 
102 /* Instruction Mnemonics */
103 #define R_REGISTER 0x00
104 #define W_REGISTER 0x20
105 #define REGISTER_MASK 0x1F
106 #define ACTIVATE 0x50
107 #define R_RX_PL_WID 0x60
108 #define R_RX_PAYLOAD 0x61
109 #define W_TX_PAYLOAD 0xA0
110 #define W_ACK_PAYLOAD 0xA8
111 #define FLUSH_TX 0xE1
112 #define FLUSH_RX 0xE2
113 #define REUSE_TX_PL 0xE3
114 #define NOP 0xFF
115 
116 /* Non-P omissions */
117 #define LNA_HCURR 0
118 
119 /* P model memory Map */
120 #define RPD 0x09
121 #define W_TX_PAYLOAD_NO_ACK 0xB0
122 
123 /* P model bit Mnemonics */
124 #define RF_DR_LOW 5
125 #define RF_DR_HIGH 3
126 #define RF_PWR_LOW 1
127 #define RF_PWR_HIGH 2